JPH11121626A - Schematic path deciding method and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire a schematic path by an accurate delay estimate, by a method wherein a schematic path of a net connected between respective cells is decided so that a delay restriction set previously is satisfied and the number of net does not exceed the set capacity. SOLUTION: In a schematic path deciding system, a schematic path is searched taking into consideration a delay value in each layer and taking into consideration a congestion degree of a wire, and wiring is performed by an accurate delay estimate so that all buses satisfy a delay restriction. This comprises an information memory part 10 storing disposed wire information related to each cell; a wire processing part 20 wiring between cells; and a wire output part 30 outputting wiring results. The wire processing part 20 performs disposition of cells, and a schematic wiring process and a detailed wiring process, and comprises a schematic lattice capacity calculation part 21, a path search part 22, a delay calculation part 23, a violation net decision part 24 and a path search cost decision part 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining a schematic path of a net connecting between cells of a chip constituting a semiconductor integrated circuit such as an LSI (Large Scale Integrated Circuit) having multiple wiring layers. And a schematic route determination method.

[0002]

2. Description of the Related Art As an automatic wiring method for automatically performing wiring between cells in a layout design of a semiconductor integrated circuit, there is an automatic placement and wiring method as disclosed in Japanese Patent Application Laid-Open No. 8-123843. FIG. 8 shows a schematic configuration of the automatic wiring system disclosed in the publication.

In FIG. 8, the automatic wiring system comprises a computer 101, netlist data 102, cell layout data 103, and wiring delay parameters 104. The computer 101 includes a delay constraint input unit 111, a cell placement unit 112, an inter-cell wiring unit 113, and a wiring delay calculation unit 11.
4. It has a constraint condition determination unit 115 and a wiring change unit 116.

The delay constraint input unit 111 provides a delay constraint for each node of the netlist. The delay constraint input unit 111 directly designates a node to which the constraint is applied by a circuit diagram editor, or links a delay simulator with a threshold value having a delay time. A process for automatically returning the nodes of the above path is performed. The cell arranging unit 112 arranges the cell layout data 103 of the cells used in the netlist data 102 in a given range.

[0005] The inter-cell wiring section 113 generates connection wiring from the connection information of the netlist data 102. The wiring delay calculation unit 114 calculates a wiring delay time using the wiring delay parameter 104 given as a wiring capacitance per unit length of a certain wiring width of each wiring layer, for example. The constraint determination unit 115 determines whether each node satisfies the constraint. The wiring changing unit 116 changes the wiring layer for a node determined not to satisfy the constraint.

In the automatic wiring system described above, when designing a layout of a semiconductor integrated circuit having, for example, three wiring layers, first, the cell arranging unit 112 arranges cells within a given range, Generates wiring between those cells. In the generation of the wiring, the selection of the wiring layer gives priority to the lower wiring. For example, the wiring of the first layer (lowest layer) is preferentially performed, and when the wiring density of the first layer is increased and the wiring satisfying the delay constraint cannot be formed in the first layer, the second layer is used. The third layer is used in order from the lower layer when the second layer becomes impossible. in this case,
As for the entire wiring result, the frequency of use becomes higher in the order of the first layer, the second layer, and the third layer. In addition, by arranging the nodes to which the delay constraint is given from the delay constraint input unit 111 in advance,
A node to which a delay constraint is applied can generate a wiring that is close to the shortest distance in a state where there is as little spatial obstacle as possible due to other wiring.

[0007] After the wiring between cells is generated, the constraint condition judging section 115 judges whether each node satisfies the constraint. If the constraint is satisfied, the wiring processing ends there. If not, the wiring layer changing unit 116 changes the wiring layer for the node determined not to satisfy the restriction.

In addition to the above automatic wiring method, Japanese Patent Laid-Open No.
There is also a general route determination method disclosed in Japanese Patent Application Laid-Open Publication No. H10-175, in which a "path with a severe delay" does not violate the delay constraint by a change at the time of general wiring processing or detailed wiring processing. FIG. 9 shows a schematic configuration of this method.

[0009] In FIG. 9, the schematic configuration of the schematic route determination method includes an information input unit 201, a delay analysis unit 202, a violation net extraction unit 203, an optimum delay value wiring layer extraction unit 204, a violation net schematic wiring processing unit 205, It comprises a control unit 200 that controls this overall.

The information input unit 201 includes, for an LSI to be processed and a printed circuit board (substrate to be processed), block arrangement information indicating the arrangement of blocks, logical connection information between blocks indicating a logical connection relationship between blocks, base and block. And base block / block physical information, which is physical information regarding the base and block, and base / block delay information which is delay information regarding the base and the block, respectively.

The delay analysis unit 202 classifies each wiring layer of the substrate to be processed into two, a vertical wiring layer and a horizontal wiring layer, based on the base / block physical information, and each of them has the largest delay value. Find the wiring layer. Further, the delay analysis unit 202 obtains the vertical length and the horizontal length of the virtual wiring length of each net of the processing target board based on the block arrangement information and the inter-block logical connection information. Then, delay analysis of each path under the virtual wiring length condition in the wiring layer having the largest delay is performed.

The violating net extraction unit 203 includes a delay analysis unit 2
A path that violates the delay constraint in the delay analysis by 02 is extracted, and violation net information indicating the nets constituting the violation path is created. The optimal delay value wiring layer extracting unit 204 obtains a wiring layer that satisfies the delay constraint by the delay analysis under the virtual wiring length condition, in which the violating path extracted by the violating net extracting unit 203 is obtained. The violating net schematic routing processing unit 205 obtains a schematic route equal to the virtual wiring length for the net indicated by the violating net information obtained by the violating net extracting unit 203, and extracts the schematic route to the optimal delay value wiring layer extraction. The assignment is made to the vertical wiring and the horizontal wiring obtained by the unit 204, and is set as a fixed one so that the assignment of the general route is not changed later.

In the above-described rough route determination method, a rough route is first obtained in the layer having the largest delay based on the net list and the delay constraint information, and the rough wiring layer has a small delay value with respect to the violating net. A schematic route is obtained by reassigning to a layer. As a result, with respect to the path of a net constituting a path with strict delay constraints, it is possible to fixedly set the wiring assignment and the path length so as not to violate the delay constraint at the stage of the general routing processing. .

[0014]

However, the above-mentioned conventional method has the following problems.

In a high-speed LSI, since the wiring pitch and the thickness are different depending on the layer, even if the wiring length is the same, the delay time differs depending on the layer used. In some cases, the difference in the delay time may be twice or more. There is. Therefore, regarding the net on the critical path, it is necessary to perform wiring in consideration of not only the wiring length but also the layer to be used.

In the automatic placement and routing method disclosed in Japanese Patent Application Laid-Open No. H8-123843, wiring of nodes with delay constraints can be routed in the shortest possible distance, and wires that do not satisfy the constraints are replaced with wires in an upper layer to delay. Although the constraint can be easily satisfied, no wiring is performed in consideration of the wiring state of the layer to be used. In this way, in the method of wiring only in the lower layer and moving to the upper layer for wiring that is caught by the delay constraint, wiring is performed without knowing what is in the upper layer, for example, when there is a power path etc. in the upper layer Causes a problem that the wiring cannot be transferred.

In the general route determination processing system disclosed in Japanese Patent Application Laid-Open No. H5-143669, it is possible to set the wiring allocation and the path length at the stage of the general wiring processing so as not to violate the delay constraint. When the layers are reassigned, only the layer is changed without changing the schematic route, and the search for the schematic route in consideration of the congestion degree of the wiring of the changed layer is not performed. As described above, if the approximate route is not determined in consideration of the congestion degree of the wiring, the wiring may not be performed in the detailed wiring processing.

The present invention solves each of the above problems, and searches for a schematic route for a net on a path that does not satisfy the delay constraint, taking into account the delay value for each layer and the congestion degree of the wiring. It is an object of the present invention to provide a rough route determination method and a rough route determination method that can obtain a rough route with accurate delay estimation so that all paths satisfy delay constraints.

[0019]

In order to achieve the above object, a schematic route determining method according to the present invention relates to a schematic route determining method for determining a schematic route of a net connecting cells of a chip constituting a semiconductor integrated circuit. The chip is finely divided into a lattice shape, the boundary of each lattice is set in advance, the capacity of a net that can be passed is set in advance, and the schematic route of the net connecting the cells is satisfied with a preset delay constraint. In addition, the number of nets actually arranged at each boundary of the grid through which the nets pass is determined so as not to exceed the capacity set at each boundary.

Further, the general route determining method according to the present invention is a general route determining method for determining a general route of a net connecting between cells of a chip constituting a semiconductor integrated circuit. For each grid boundary in each of a plurality of wiring layers constituting the chip, the capacity of a net that can be passed is set in advance, the cost of each layer used as a priority order of the plurality of wiring layers, and the path of the net The overflow cost for limiting the length is set to a predetermined value, and the number of overflows of the net at each boundary of the lattice through which the net passes, and the wiring length of the net in the wiring layer through which the net passes, are as follows: The route that minimizes the net cost obtained from the equation is searched for each of the nets connecting the cells, and Cost = (number of overflows) × (overflow cost) + {(wiring length of each layer) × (cost of each layer)}

If there is a net that does not satisfy the delay constraint set in advance, the overflow cost is reduced so that the net path length is shortened and the plurality of nets are set so that the priority of the upper layer becomes higher. The cost of the upper layer out of the layers is reduced, and the route with the minimum net cost obtained by the above equation is searched again. If there is an overflowing net, the path length of the net is The overflow cost is increased so as to be longer, and a route that minimizes the net cost obtained by the above equation is searched again.

In the above case, when there is a net that does not satisfy the delay constraint, the general route determining method is characterized in that the overflow cost and the upper layer cost are set to be smaller as the violated delay is larger. You may make it set so that it may become.

Also, for a specific net, the cost of the upper layer of the plurality of wiring layers is set to be smaller than the cost of the upper layer of the other nets, and the route that minimizes the net cost determined by the above equation is determined. You may make it search.

According to the general route determination method of the present invention, an information storage means in which connection information and delay constraints of a net connecting between cells of a chip constituting a semiconductor integrated circuit are stored in advance, and the chip is finely divided into a lattice. Separately, the capacity of a net that can be passed is determined in advance for each grid boundary in a plurality of wiring layers constituting the chip, and the cells are connected based on the information stored in the information storage means. Wiring that determines a schematic route of a net so as to satisfy the delay constraint and to prevent the number of nets actually arranged at each boundary of a lattice through which the net passes from exceeding the capacity set at each boundary. And processing means.

In the above case, the information storage means includes a default cost in which the cost of each layer used as a priority order of the plurality of wiring layers and an overflow cost for limiting the path length of the net are set to predetermined values. A route search cost that is set when the delay constraint is violated, wherein the overflow cost is reduced so that the net path length is shorter than the default cost according to the violation delay, and the priority of the upper layer is higher. And at least one route search cost in which the cost of the upper layer is reduced in advance, and the wiring processing unit determines, for a boundary of each grid in the plurality of wiring layers,
Capacity calculation that sets the capacity of nets that can pass through in advance, and calculates the remaining capacity by subtracting the number of actually arranged nets from the capacity set at each boundary of the grid through which the net passes Means, a route search means for searching a schematic route of a net between the cells, a delay calculation means for calculating a delay of a route of the net searched by the route search means, and a capacity calculation means and a delay calculation means. A violating net determining unit that determines whether a calculation overflow has occurred or does not violate the delay constraint for a route of each net searched by the route searching unit based on the calculation result; The route search cost according to the violation delay is stored in the storage means for the net determined to have not satisfied the delay constraint by the means. A route search cost determining unit that determines from the search cost, and increases the overflow cost of the default cost and the route search cost stored in the storage unit when it is determined that the overflow has occurred in the violating net determination unit; The route search means searches for a route having a minimum net cost determined by the following equation using the default cost stored in the storage means, and the net cost = (number of overflows) × (overflow (Cost) + {(Wiring length of each layer) × (Cost of each layer)} For the net determined by the violating net determination unit to not satisfy the delay constraint, the route search set by the route search cost determination unit Re-searching the route that minimizes the net cost obtained by the above equation using the cost, If it is determined that there is an overflow, the route search cost determination means uses the default cost and the route search cost whose overflow cost has been increased to re-search for a route that minimizes the net cost obtained by the above equation. May be configured.

Further, the route search cost stored in the storage means in advance may be set such that a net having a larger violation delay has a smaller overflow cost and a higher layer cost.

Further, for a specific net, a second default cost in which an upper layer cost of the plurality of wiring layers is set smaller than an upper layer cost of the other nets is stored in the information storage means in advance, The route search means may determine the approximate route of the specific net by searching for a route that minimizes the net cost obtained by the equation using the second default cost.

(Operation) In the present invention as described above, the capacity of a net that can pass through each grid boundary is set, and the route of the net is determined so as not to exceed the capacity. Is determined in consideration of the general route of the net. Therefore, wiring cannot be transferred to the upper layer due to a power supply path in the upper layer as in the conventional method, or detailed wiring cannot be performed because a schematic route is not obtained in consideration of the degree of congestion of the wiring. There is no problem such as that.

Also, in the present invention, a route that minimizes the net cost obtained by the following equation is searched for using the default cost, and the net cost = (number of overflows) × (overflow cost) + Σ ｛(the wiring length of each layer) ) × (cost of each layer)｝ For the delay violation net, the net cost obtained by the above equation using the route search cost set such that the overflow cost and the upper layer cost are smaller than the default cost according to the violation delay is the minimum. Route is rediscovered,
When the overflow occurs, the overflow cost of the default cost and the overflow cost of the route search cost are respectively increased, and the route with the minimum net cost obtained by the above equation is searched again. In the re-search for the route of the delay violation net, the shortest route is searched by reducing the overflow cost, and the upper layer having a small delay constraint is preferentially used by further reducing the cost of the upper layer. If the route overflows, the route cost is re-searched while increasing the overflow cost.
As the overflow cost increases, the path length increases. That is, a bypass route is searched. As described above, in the present invention, the shortest path is searched for the delay violation net using the upper layer having a small delay constraint, and when the net overflows, the detour is searched. A search for a schematic wiring path is performed in consideration of the degree of wiring congestion.

Further, in the present invention, the route search cost is set such that the overflow cost and the cost of the upper layer become smaller for a net having a larger violation delay, so that a net having a larger violation delay is preferentially used for the upper layer. ,
A route is searched for at the shortest distance. As a result, it is possible to search for a schematic routing path in consideration of the delay value for each layer for nets on paths that do not satisfy the delay constraint, and it is possible to use different layers for nets with severe delay constraints and nets with less severe delay constraints become.

[0031]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a schematic route determination system according to the present invention. This method searches for a schematic route that takes into account the delay value of each layer and also the degree of congestion of the wiring, and performs wiring with accurate delay estimation so that all paths satisfy the delay constraint. so,
The configuration includes an information storage unit 10 in which arrangement and wiring information relating to each cell is stored, and a wiring processing unit 20 for performing wiring between cells.
And a wiring result output unit 30 that outputs a wiring result.

The information storage unit 10 stores a netlist 11 which is cell connection information, and a cell information file 1 which stores information on cells, such as the position and number of internal wiring and connection terminals.
2. It has an arrangement information file 13 in which information on cell arrangement is stored, and a delay constraint information file 14 in which information on delay constraint is stored.

The wiring processing unit 20 includes the information storage unit 10 described above.
The cell arrangement, the general routing process, and the detailed routing process are performed based on the above information. The general lattice capacity calculation unit 21, the route search unit 22, the delay calculation unit 23, and the violating net determination unit 2
4. A plurality of processing units of the route search cost determination unit 25.

The approximate grid capacity calculating section 21 is for considering the degree of congestion of wiring. For example, as shown in FIG. 2, the rough grid capacitance calculating unit 21 finely divides a chip in a horizontal direction and a vertical direction (divides the chip into grids) and, for each grid boundary, the number of wires (capacity) that can be passed. ) Is set in advance. Then, for each boundary of the grid through which the net passes, the remaining capacity is calculated by subtracting the number of nets actually arranged from the capacity set at the boundary. In the calculation of the capacitance, for example, when the capacitance at the boundary is set to seven, when there are three wirings actually arranged at the boundary, the remaining capacitance at the boundary is four. Here, the actually arranged wirings include wirings that are determined to be used in advance, such as power supply paths and internal wirings of cells. For example, as shown in FIG.
In the case where the power supply path 42 is disposed at the boundary A, a portion overlapping the power supply path 42 (a wiring prohibited portion) may be wired. Since it is not possible, the number of lines from which the amount is subtracted is calculated as the remaining capacity of the boundary A. here,
Information about a wiring prohibited part such as a power supply path and an internal wiring of a cell is stored in the information storage unit 10 in advance, and the approximate grid capacitance calculating unit 21 calculates the capacity based on the wiring prohibited area stored in the information storage unit 10. calculate. If the number of actually arranged wirings (flow) exceeds the number of wirings set at the boundary (overflow), it is determined that the boundary cannot be routed, and if not, wiring is performed at the boundary. Judge that there is room to pass through. The desirable size of the grid that finely divides the chip in the horizontal direction and the vertical direction is specifically, in terms of the number of wiring tracks that can divide the chip in the horizontal and vertical directions, in both the horizontal and vertical directions. Although the size is divided at intervals of 15 to 20, the size is not particularly limited.

The route search unit 22 searches for a schematic route of a net between cells. In the route search by the route search unit 22, the cost (net cost) of the wiring route for each net is calculated as: net cost = (number of overflows) × (overflow cost) + {(wire length of each layer) × (cost of each layer)} Calculate by (1) and search for the route with the minimum cost. here,
The overflow cost is a coefficient that is multiplied by the number of overflows at each boundary of the grid located on the path of each net. The smaller this value is, the shorter the path length is. The cost of a layer is a coefficient multiplied by the wiring length of each layer serving as a route of each net, and a layer having a smaller value is used preferentially. Here, a default cost in which the overflow cost and the cost of each layer are set to default values, and a route search cost in which the overflow cost and the cost of each layer are set according to the violation delay amount (the cost set for the delay constraint violation net) ) Are stored in the information storage unit 10 in advance, and the route search unit 22 first searches the route of each net at a default cost (overflow cost and a reference value of the cost of each layer), as described later. With respect to the net violating the delay constraint, a route search is performed again at a route search cost according to the violation delay.

The delay calculating section 23 calculates the delay of the route of each net searched by the route searching section 22. The violating net determination unit 24 checks whether the route of each net searched by the route searching unit 22 does not overflow or does not violate the delay constraint, and regards any of the nets as a violating net. judge.

The route search cost determination unit 25 determines the route search cost according to the violation delay for the route of the net for which the violation constraint is determined by the violation net determination unit 24. Specifically, the route search cost determination unit 25 determines the information storage unit 1 according to the delay result calculated by the delay calculation unit 23.
The route search cost is determined from the route search costs stored in 0. Further, the route search cost determination unit 25
When overflow occurs, the overflow cost is increased for each of the default cost and the route search cost stored in the information storage unit 10.

The above-described route search unit 22 uses the route search cost set by the route search cost determination unit 25 for the nets determined by the violating net determination unit 24 as not satisfying the delay constraint. The route with the minimum net cost obtained by Expression 1 is re-searched, and if it is determined by the violating net determination unit 24 that the route has overflown, the default cost and the default cost whose overflow cost has been increased by the route search cost determination unit 25 are determined. Using the route search cost, the route with the minimum net cost obtained by the above equation 1 is searched again.

Next, the procedure of a route search process performed in the above-described general route determination method will be described with reference to FIG.

First, the approximate grid capacity calculator 21 calculates the capacity of the boundary of each grid based on the given information (eg, information on the initial wiring such as the power supply path) (step S10). Subsequently, the route search unit 22 searches for the route of each net at the default cost prepared in the information storage unit 10 and searches for the route with the minimum cost determined by the above-described Expression 1 (step S11). ).

When the route search is performed by the route search unit 22 to obtain an initial route, the delay calculation unit 22 calculates the delay of the route of each net (step S12).
Then, based on the result of the delay calculation, the violating net determination unit 24 determines whether there is a net that does not satisfy the delay constraint (step S13). If there is a net that violates the delay constraint, the route search cost determining unit 25 determines a route search cost according to the violation delay for the violating net, and the route search unit 22 calculates the route search cost based on the determined route search cost. The route of the net violating the delay constraint is searched again (step S14). Also in the route re-search at this time, the route with the minimum cost obtained by the above equation 1 is searched.

In step S14, if there is no net that violates the delay constraint, the violating net determination unit 24 determines whether there is an overflowing net (step S15). When there is an overflowing net, the route search cost determination unit 25 increases the overflow cost of the default cost and the route search cost stored in the information storage unit 10, and returns to step S11 again (step S15). If there is no overflowing net, the process ends.

Hereinafter, the above-described route search process will be described with a more specific example.

Here, as shown in FIG. 5, a grid 51 is set by finely dividing the chip 50 in the horizontal direction and the vertical direction. The first and third layers are used for the horizontal wiring, and the vertical wiring is used. Is used for the second layer. The capacity preset in the boundaries A and B is three in the first layer and one in the third layer. Information about three nets A, B, and C is prepared in the net list, and the route search unit 22 sets an initial route (a route obtained at a preset default cost) as shown in FIG. ing. Here, the costs used for the route search include a default cost and a violation delay 1 as shown in FIG.
A cost of less than ns and a cost of a violation delay of 1 ns or more are set in advance. Furthermore, here, 20 times are set as the number of times of improvement for designating how many times the processing of steps S11 to S16 shown in FIG. 4 is repeated. In the following description, for the illustrated net, in the horizontal direction, a solid line indicates a route wired in the first layer, and a broken line indicates a route wired in the third layer.

First, the initial route is determined by calculating the capacity of the boundary of each grid based on the initial wiring. In the example shown in FIG. 5, steps S10 and S1 shown in FIG.
Since the processing of No. 1 has already been performed and the initial route has been searched, the processing after step S12 will be described here.

When the initial routes for the nets A, B, and C are searched, the processes of steps S12 to S16 shown in FIG. 4 are sequentially performed for the nets A, B, and C, respectively. Here, in the process of step S12, net A satisfies the delay constraint, net B violates 0.5 ns,
Net C is described as violating 2 ns.

First, for the net A, steps S12-
The processing of S14 is performed. Since this net A satisfies the delay constraint, its route remains the route shown in FIG.

Subsequently, step S12 is performed for the net B.
To S14. Since the net B violates the delay of 0.5 ns, the cost of the violation delay of less than 1 ns is determined as the route search cost by the process of step S14, and the route search is performed again based on the cost (peeling off). Rewiring). In this route search, the cost of net B = 0 (the number of overflows) × 2 (the overflow cost) +3 (the wiring length of the third layer) × 5 (the third
The minimum cost path given by (layer cost) +2 (second layer wiring length) × 5 (second layer cost) is searched. Here, the number of overflows is the sum of the number of overflows at the present time at the boundaries A and B of the third layer. The wiring length of each layer is the current wiring length in each layer of the route of the net to be searched. Here, the wiring length is represented by the number of grids passing through the path (the number of grids spanning the path). In this route search, as shown in FIG. 7A, a route in which the horizontal wiring is shifted from the first layer to the third layer is searched. When the route is searched, the delay for this route is calculated, and if the delay constraint is not satisfied, the route search is performed again at a route search cost corresponding to the violation delay. Here, it is assumed that the delay constraint is satisfied, and the process proceeds to the next net C.

Since the net C violates 2 ns,
By the process of step S14, a cost of 1 ns or more as a violation delay is determined as a route search cost, and a route search is performed again based on the cost (peeling and rewiring). In this route search, as in the case of the net B described above, the cost of the net C = 2 (the number of overflows) × 1 (the overflow cost) +3 (the wiring length of the third layer) × 2 (the third
The least cost path given by (layer cost) is searched. Here, the number of overflows is the sum of the number of overflows at each of the boundaries A and B passing through the net. Here, the capacity of both the boundaries A and B of the third layer is one, and the route of the net C is already routed through the boundaries A and B as described above. Those boundaries A, B
When wiring is performed so as to pass through, one overflow occurs at each of the boundaries A and B, and the sum of the overflow numbers at the present time at the boundaries A and B is two. In this route search, for example, as shown in FIG. 7B, a route in which the horizontal wiring is shifted from the first layer to the third layer is searched. When the route is searched, the delay for this route is calculated, and if the delay constraint is not satisfied, the route search is performed again at a route search cost corresponding to the violation delay. Here, it is assumed that the delay constraint is satisfied, and the processes of the following steps S15 and S16 are sequentially performed for each of the nets A to C.

At this point, the route relating to the net A is wired so as to pass through the boundaries A and B of the first layer (see FIG. 7B). There are three capacitors at the boundaries A and B of the first layer, and no nets other than the net A are wired at these boundaries A and B. Therefore, the net A does not overflow, and the route of the net A remains unchanged.

The route for the net B is wired so as to pass through the boundaries A and B of the third layer as shown in FIG. The capacity of both the boundaries A and B of the third layer is one, and a route related to the net C in addition to the net B is wired to the boundaries A and B of the third layer. Therefore, in the route of the net B, one overflow occurs at each of the boundaries A and B of the third layer, and it is determined that the net B has overflown. If it is determined that an overflow has occurred, in the process of step S16, the overflow cost of the default cost and the route search cost set in accordance with each violation delay is amplified, for example, by a factor of two, and again set in step S11. The route search for the net B is performed at the default cost. In this route search, for example, as shown in FIG. 7C, a route in which the horizontal wiring passes the boundaries C and D of the third layer is searched. Then, the processes of steps S12 to S15 are performed successively, and if the searched route does not satisfy the delay constraint, the route is searched again at the route search cost newly set in the process of step S16. Is performed. The search for the route for the net B is performed until it is determined that the delay constraint is satisfied and no overflow occurs.

When it is determined that the route to the net B satisfies the delay constraint and does not overflow, it is determined whether the net C overflows. The route for the net C is the boundary A, B of the third layer.
(FIG. 7B)
reference). The capacity at the boundaries A and B of the third layer is one, and a new route is searched for the net B by the above-described processing. Will not have been. Therefore, the net C does not overflow, and the route of the net C remains unchanged. In addition,
When a route of another net exists at the boundary C or D and overflows, a new route is searched for with a default cost whose overflow cost is amplified as in the case of the net B described above. If the route violates the delay constraint, the route is re-searched using the route search cost with the amplified overflow cost.

When the route (schematic route) of each of the nets A to C is obtained as described above, detailed wiring is performed while observing the obtained rough route. In addition, each of the nets A to
The order of the route search of C is not particularly limited, and is determined according to the design.

In the present embodiment, the initial route is obtained at the default cost for all nets. However, the present invention is not limited to this. For example, only for a specific net (for example, a net having a large delay such as an inter-block net), a route search may be performed at a designated cost in which the upper-layer cost is smaller than the default cost. In this case, a route with the minimum cost determined by the above equation 1 is also searched.

[0056]

According to the present invention configured as described above, for a net on a path that does not satisfy the delay constraint, the delay value of each layer is taken into consideration and the congestion degree of the wiring is taken into consideration. A rough route search is performed, and layers are selectively used for nets with severe delay constraints and less severe ones.Therefore, routing can be performed with accurate delay estimation so that all paths satisfy delay constraints. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a schematic route determination method according to the present invention.

FIG. 2 is a diagram showing an example in which chips are divided in a grid pattern.

FIG. 3 is a diagram illustrating an example in which a wiring overlaps a power supply path.

FIG. 4 is a flowchart showing a route search processing procedure performed in the schematic route determination method shown in FIG. 1;

FIG. 5 is a diagram illustrating an example of an initial route.

FIG. 6 is a diagram illustrating an example of a default cost, a violation delay less than 1 ns cost, and a violation delay 1 ns or more cost.

FIGS. 7A to 7C are diagrams illustrating an example of a route searched in each route search process.

FIG. 8 is a block diagram showing a schematic configuration of an automatic wiring system disclosed in JP-A-8-123843.

FIG. 9 is a block diagram showing a schematic configuration of a schematic route determination method disclosed in Japanese Patent Application Laid-Open No. Hei 5-13669;

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 information storage unit 11 netlist 12 cell information file 13 placement information file 14 delay constraint information file 20 wiring processing unit 21 approximate grid capacity calculation unit 22 route search unit 23 delay calculation unit 24 violating net determination unit 25 route search cost determination unit 30 Wiring result output section

Claims (8)

[Claims] 1. A schematic path determining method for determining a schematic path of a net connecting cells of a chip constituting a semiconductor integrated circuit, wherein the chip is finely divided into grids, and a boundary of each grid can be passed. The capacity of the net is set in advance, and the schematic route of the net connecting the cells satisfies the delay constraint set in advance, and the net of the net actually arranged at each boundary of the grid through which the net passes. A method for determining a schematic route, wherein the number is determined so as not to exceed a capacity set at each boundary. 2. A general path determining method for determining a general path of a net connecting between cells of a chip constituting a semiconductor integrated circuit, comprising: a plurality of wiring layers constituting the chip by finely dividing the chip into a lattice shape; For each of the lattice boundaries in each of the above, the capacity of the net that can pass through is set in advance, and the cost of each layer used as the priority order of the plurality of wiring layers and the overflow cost that limits the path length of the net are respectively By setting the value to a predetermined value, the net cost obtained from the following equation is minimized from the number of overflows of the net at each boundary of the grid through which the net passes and the wiring length of the net in the wiring layer through which the net passes. A route is searched for each of the nets connecting the cells, and net cost = (number of overflows) × (Overflow cost) + {(wire length of each layer) × (cost of each layer)} If there is a net that does not satisfy the delay constraint set in advance, the overflow cost is set so that the path length of the net is shortened. Is reduced, and the cost of the upper layer of the plurality of layers is reduced so that the priority of the upper layer becomes higher. In the case where there is a general route, the overflow cost is increased so as to increase the route length of the net, and a route that minimizes the net cost obtained by the above equation is searched again. Decision method. 3. The general route determination method according to claim 2, wherein, if there is a net that does not satisfy the delay constraint, the overflow cost and the upper-layer cost are set to be smaller as the violated delay is larger. A schematic route determination method characterized by the above-mentioned. 4. The general route determination method according to claim 2, wherein, for a specific net, a cost of an upper layer of the plurality of wiring layers is set smaller than a cost of an upper layer of another net. A general route determination method characterized by searching for a route that minimizes the net cost obtained by the equation. 5. An information storage means in which connection information and a delay constraint of a net connecting between cells of a chip constituting a semiconductor integrated circuit are stored in advance, and said chip is finely divided in a grid to constitute said chip. For each grid boundary in a plurality of wiring layers, the capacity of a net that can pass is determined in advance, and based on the information stored in the information storage unit, the schematic route of the net connecting the cells is defined as Wiring processing means that satisfies the delay constraint and determines that the number of nets actually arranged at each boundary of the grid through which the nets pass does not exceed the capacity set at each boundary. Schematic route determination method to be characterized. 6. The schematic route determination method according to claim 5, wherein the information storage means calculates a cost of each layer used as a priority of the plurality of wiring layers and an overflow cost for limiting a route length of a net. A default cost set to a predetermined value, and a route search cost set when the delay constraint is violated, and an overflow cost such that a net path length is shorter than the default cost according to a violation delay. And at least one route search cost in which the cost of the upper layer is reduced so as to increase the priority of the upper layer, and the wiring processing means is configured to store the boundary of each grid in the plurality of wiring layers. The capacity of the net that can pass through is set in advance, and each boundary of the grid Capacity calculating means for calculating a remaining capacity obtained by subtracting the number of nets actually arranged from the capacity set at the boundary; a route searching means for searching a schematic route of a net between the cells; Delay calculating means for calculating the delay of the route of the net searched by the searching means; calculating overflow for the route of each net searched by the route searching means based on the calculation results of the capacity calculating means and the delay calculating means. Violation net determination means for determining whether the delay constraint is not violated or not, and for a net determined to be not satisfying the delay constraint by the violation net determination means, according to the violation delay. The determined route search cost is determined from the route search cost stored in the storage unit, and the violation net determination unit determines that the overflow has occurred. A route search cost determining means for respectively increasing a default cost stored in the storage means and an overflow cost of the route search cost, wherein the route search means has a default cost stored in the storage means. Is used to search for a route that minimizes the net cost determined by the following equation: net cost = (number of overflows) × (overflow cost) + {(wire length of each layer) × (cost of each layer)} For the nets that are determined not to satisfy the delay constraint by the determining means, a route that minimizes the net cost determined by the above equation is searched again using the route search cost set by the route search cost determining means. If it is determined by the violating net determining means that an overflow has occurred, the route search cost determining means determines that an overflow has occurred. Summary path determination method, characterized in that Kosuto net cost calculated by the equation using the default cost and the route search cost is increased to re-search a route that minimizes. 7. The schematic route determination method according to claim 6, wherein the route search cost stored in advance in said storage means is set such that an overflow cost and an upper-layer cost are smaller for a net having a larger violation delay. General route determination method characterized by the following. 8. The general route determination method according to claim 6, wherein a cost of an upper layer of the plurality of wiring layers is set to be smaller than a cost of an upper layer of another net for a specific net. A default cost is stored in the information storage unit in advance, and the route search unit determines a schematic route of the specific net,
A method for determining a general route, wherein the second default cost is used to search for a route that minimizes the net cost obtained by the above formula.