JPH01243540A - Wiring of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To avoid that wiring parts are crossed near an adjacent part between channels by a method wherein, when the wiring parts of adjacent channels sandwiching a channel boundary are to be processed separately, the relative order of channel boundary terminals on the channel boundary is decided. CONSTITUTION:An appoximate wiring route at each signal line including a setting-up operation of channel boundary terminals at a channel boundary as a junction part between a channel and another channel is decided. A collection of the route requested to be connected only at the upper part from the channel boundary on the vertical channel side is designated as a group U. A collection of the route requested to be connected only at the lower part from the channel boundary on the vertical channel side is designated as a group D. In the case of the channel boundary in the vertical direction, a relative order relationship is set in such a way that an arbitrary channel boundary terminal belonging to the group U is situated at the upper part of an arbitrary channel boundary terminal belonging to the group D. While the relative order relationship of the channel boundary terminals is being satisfied, a detailed wiring operation at each channel is executed in all channels.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a wiring method between blocks in a building block layout of a semiconductor integrated circuit.

(Prior art) The h-circuit is divided into multiple functional units using a building block layout, then these are individually laid out as blocks, and finally the placement of each block on the chip and the wiring between the blocks are performed. Do this.

In wiring between blocks, it is common to divide the wiring area into a plurality of channels as shown in FIG. 2, and then process the detailed wiring after determining the general wiring route. At that time, a virtual terminal (channel boundary terminal) is set on the channel boundary between adjacent channels, and its exact position is determined first on the channel side where wiring processing is to be performed.
The wiring is drawn out with reference to that position on the other adjacent channel side.

At this time, if wiring is performed without any consideration to the positional relationship between the channel boundary terminals, the wiring will cross near the channel boundary, as shown in the example shown in Figure 6, and the channel width will increase. There was a problem with inviting people.

(Problems to be Solved by the Invention) The present invention provides a method for avoiding an increase in the channel width due to wiring crossings in adjacent portions of the channel, thereby improving the degree of integration. The purpose is to

[Structure of the invention]

(Means for solving the problem) On the channel boundary connecting channels, a partial order relative positional relationship is determined for the channel boundary terminals set for the signal line that crosses the boundary. , perform detailed wiring for each channel while maintaining their positional relationships.

In this order relationship, the way the wires are drawn out from the channel boundary is examined and determined so that the wires do not cross in the vicinity of the channel boundary.

In addition, when investigating how to draw out wiring from channel boundaries, estimate the channel width in advance in order to reduce the deviation from the detailed wiring processing time, and calculate the position of each block, block terminal position, and channel boundary position. Let's estimate.

(Function) When processing the wiring of adjacent channels across a channel boundary separately, by determining the relative order of the channel boundary terminals on the channel boundary, it is possible to Wiring crossing can be avoided.

(Example) Below, an example of the wiring method according to the present invention will be explained according to the processing procedure. (See FIG. 1) It is assumed that the layout within a block, the approximate location of each block, and the channels between blocks have already been defined.

8TEP 1 Determination of general wiring route Here, for each signal line, block passing through the wire for connecting between the terminals of Determine the channel and cross the route. the channel of that signal on the channel boundary Set the border terminals.

5TEP2 Determination of channel wiring order Determine the detailed wiring processing order for multiple inter-block channels based on their adjacency relationships.

5TBP3 Estimating Channel Width The degree of wiring congestion for each channel is determined based on the approximate wiring route for each signal line, and the channel width is estimated from this value.

The wiring congestion degree and channel width are determined by the empirical formula It is closely related.

5TEP4 Calculate block placement position Calculate block placement position using the estimated channel width.

5TEP5 Calculate terminal position of block Calculate the position of the terminal based on the arrangement position of the block. This position is an estimated value that depends on the accuracy of channel width estimation, but it is necessary for grouping the channel boundary terminals in the next 8TEP6, and it must have sufficient accuracy for that process. It's good to have.

5TEP6 Grouping of channel boundary terminals performs relative ordering grouping for channel boundary terminals.

Below, the channel boundaries are vertically This will be explained using the case of running as an example. (No. (See Figure 3) The two forming the boundary of this channel Among the channels, check horizontal channel 8. Channel H1 Vertical Channel 9 Let it be V.

y position at the lower and upper ends of channel boundary 6 Let the marks be yl and y2, respectively.

At this time, the channel that satisfies the following conditions Find the set of boundary terminals.

NU: Connected to the connection terminal within channel V. And its y-coordinate yT is There is one or more things with yT≧y2. , and yT<yl is a person Channels that connect to unusual signals border terminal.

ND: Connected to the connection terminal within channel V. And its y-coordinate yT is There is one or more things with yT≦y1. and YT > Yz. Channels that connect to unusual signals border terminal.

For the channel boundary terminal, the above two Find the terminals that belong to the group of is the processing of 5T14.

In Figure 3, 10 is an example of the set NU 11 is an example of ND. just However, according to the 12, it belongs to both NU and ND. There are some that don't.

Note that when the channel boundary runs in the horizontal direction, the coordinates are rotated by 906 and the same processing as above is performed.

S'l'EP7 Determining the relative order of channel boundary terminals The case where the channel boundaries in FIG. 3 run in the vertical direction will be explained as an example.

For channel boundary terminal n U belonging to NU and channel boundary terminal nD belonging to l'jJD, n
A relative positional ordering in which g is above nD is set for all set element lines. At this time, no particular ordering is performed between the elements of NU or between the elements of ND. Therefore, this is a partial relative position.

Note that when the channel boundary runs in the horizontal direction, the coordinates are rotated by 90'' and the same processing as described above is performed.

5TEP6.5TEP7 processing is executed for all channel boundaries.

8TEP8 The unprocessed channels of detailed wiring are drawn out one by one, and the detailed wiring within the channels is executed. The processing order is based on the order determined in 5TEP2, and all channels are executed and finished. At this time, processing is performed taking into account the relative positional order of the channel boundary terminals determined in 5TEP7.

FIG. 4 shows an embodiment according to the present invention.

In this example, a channel boundary terminal belonging to NU, that is, a channel boundary terminal corresponding to a signal connected only above the channel boundary in the vertical channel, and a channel boundary terminal belonging to ND, that is, a channel boundary terminal corresponding to a signal connected only above the channel boundary in the vertical channel, The relative order is determined so that the former is above and the latter is below, with the channel boundary terminal corresponding to the signal that is only connected to the channel boundary terminal, so that the wiring of the two does not cross on the vertical channel side after detailed wiring. .

Note that channel boundary terminals that do not belong to NU or ND are not particularly ordered because changing their position on the channel boundary does not contribute to a change in the degree of wiring congestion.

[Effects of the Invention] - The main things that cause wire crossings near channel boundaries are the signal lines that connect to the channel boundary terminals belonging to the above NU and ND, so the relative positions of the channel boundary terminals should be examined in detail. By determining this before wiring, it is possible to eliminate this wiring intersection and suppress an increase in the number of channel tracks.

In addition, when determining the relative positions of channel boundary terminals, a very loose partial order is used instead of the full order, so there are only minor constraints on detailed wiring processing for channels that have channel boundaries on the short sides of the channel. The number of tracks can be made almost the same as when the channel boundary terminals are not ordered.

In this way, the increase in channel width can be suppressed and the degree of integration can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the processing flow of the present invention, FIG. 2 is a diagram showing an example of the structure of a chip, FIG. 3 is a diagram for explaining grouping of channel boundary terminals, and FIG. 4 is a diagram showing the process flow of the present invention. FIG. 5 is a diagram showing a conventional processing flow, and FIG. 6 is a diagram showing problems with the conventional method. 1...Block 2...Input/output circuit block 3...
...Channel 4...Block terminal 5...Wiring path 6...Channel boundary 7...・Channel boundary terminal 8...
...Horizontal channel 9...Vertical channel 10...Signal 11 with channel boundary terminal belonging to NU...Channel belonging to ND Signal with a boundary terminal 12...Signal with a channel boundary terminal that does not belong to either NU or ND

Claims (1)

[Claims] In inter-block wiring processing, multiple circuit blocks for which internal layout has been completed are placed on a semiconductor chip, the wiring area for connections between the blocks is divided into multiple channels, and the channels are sequentially routed. The process of determining the approximate wiring route for each signal line, including setting the channel boundary terminal at the channel boundary, which is the joint part of In this case, among the channel boundary terminals set for signal lines drawn from the horizontal channel side to the vertical channel side, the set of those that require connection only upward from the channel boundary on the vertical channel side is group U, and the vertical channel A set of wires that require connection only downwards from the channel boundary on the side is classified as Group D, and in the case of a horizontal channel boundary, a channel set for a signal line drawn from the vertical channel side to the horizontal channel side. Among the boundary terminals, group L is a set of boundary terminals that require connection only to the left of the channel boundary on the horizontal channel side, and group R is a set of boundary terminals that require connection only to the right of the channel boundary on the horizontal channel side. The process of classifying is performed on all channel boundaries, and in the case of vertical channel boundaries, the relative ordering is performed so that any channel boundary terminal belonging to group U is located above any channel boundary terminal belonging to group D. In the case of horizontal channel boundaries, a process is performed in which a relative order relationship is set so that any channel boundary terminal belonging to group R is located to the right of any channel boundary terminal belonging to group L. , a step of performing detailed wiring for each channel for all channels while satisfying the relative positional relationship of the channel boundary terminals set in the step, wiring method.