JP3180968B2 - Wiring method in IC - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interactive design system for arranging elements in a semiconductor integrated circuit and performing multilayer wiring, and more particularly to a wiring method in an IC for efficiently performing multilayer wiring.

[0002]

2. Description of the Related Art At present, a so-called CAD (Computer Aided Design) system is actively used in various fields as a computer-based design system, and is becoming indispensable. As is well known, this CAD system
A designer performs design while communicating with a computer via a visible device such as a display device, and thereby a considerable part of the design process can be automated.

[0003] The CAD is no exception in the semiconductor field, and is especially indispensable when creating layout patterns and wiring in an integrated circuit (hereinafter referred to as IC).

[0004] Usually, such a CAD system uses a concept of a layer (layer) and can cope with multilayer wiring. According to this multilayer wiring, the degree of freedom and the degree of integration of the wiring can be improved. In the case of performing actual wiring in a system using this layer, conventionally, for example, “V
As described in "LSI Design I" (Iwanami Shoten Makoto Watanabe et al.), Techniques such as a line segment search method, a maze method, and a channel wiring method have been used. Of these, in the channel wiring method, wiring in the horizontal and vertical directions is generally referred to as the first layer,
There is a restriction that it is assigned to the second layer. In addition, although the line segment search method and the maze method define a method for determining a wiring route between two points, there is no established technology for the correspondence of layers, and there is a problem in which wiring of each conductor is caused by other wiring or the like. At that time, the layer was changed appropriately.

[0005]

However, in these methods, since the layer is changed as needed in the middle of each wiring as described above, there are the following problems.

(I) Since the layer is changed each time according to the local situation, the layer switching is not orderly.

(Ii) By performing unnecessary layer switching, many vias for connecting layers are generated.

For this reason, there has been a problem that the layout becomes complicated and it is difficult to design a compact circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is an object of the present invention to provide a wiring method in an IC which can eliminate unnecessary layer switching and perform an orderly and compact circuit design without depending on a wiring order. The purpose is to provide.

[0010]

According to the present invention, there is provided an IC wiring method in an interactive design system for arranging elements in a semiconductor integrated circuit and performing multilayer wiring using a display device. In step (2), global wiring for roughly determining a connection path between terminals to be connected to each other is performed. (Ii) In a second step, in one layer, based on the connection path determined by global wiring, (Iii) In the third step, the layers are distributed to the respective layers so that the wirings made in the detailed wiring step do not interfere with each other. Things. Further, a first method of wiring in an IC according to the present invention is described.
The step is to overlap multiple wires that take the same connection path.
Allows for global wiring to determine the connection path.
You. Further, the second step of the wiring method in an IC according to the present invention is described.
The tips allow each wire to cross each other within one layer
Detailed wiring for assigning tracks between children with individual conductors
Is what you do.

[0011]

According to the method for wiring in an IC according to the present invention, a single layer
By allocating each wiring to each layer after performing global wiring and detailed wiring, it is possible to optimize layer allocation without depending on the wiring order in detailed wiring. Ma
The detailed wiring of the wiring method in an IC according to the present invention is the final wiring method.
Allow for crossover between wires while taking into account typical wiring conditions
Useless layer switching due to wiring order due to wiring
Can be eliminated.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

Here, a description will be given assuming that an IC pattern layout as shown in FIG. 2 is formed on a display device screen of an IC pattern design system to which the intra-IC wiring method according to the present invention is applied. As shown in this figure, hatched portions 11 and the like indicate input / output terminals. The white rectangular blocks 12 and the like represent functional blocks each having a predetermined function. Here, the predetermined function refers to various functions such as input / output, amplification, control, and the like, and each block includes a large number of gate elements and the like.

Here, it is assumed that the layout work of the functional blocks has already been completed in the steps of IC pattern design, and then the work of actually wiring between these functional blocks or between the input / output terminals is performed. Shall be.

Hereinafter, this operation will be described with reference to FIG. First, as shown in FIG. 2, when the arrangement of the functional blocks is completed (Step S101 in FIG. 1), next, global wiring is performed (Step S102). Here, the global wiring refers to a wiring process for roughly determining a wiring path for connecting predetermined terminals of each functional block, and a stage in which a plurality of wirings are allowed to overlap as long as the same path is taken. Wiring. In other words, multiple wirings that take the same connection path
Allow wiring and determine the connection route
You.

When the global wiring is completed, the screen is displayed as shown in FIG. As shown in this figure,
The wiring connecting each functional block or terminal is expressed as one line as long as the same route is taken. Therefore, in this state, it is not possible to grasp the actual connection relationship between the individual input / output terminals or the terminals of the functional blocks. However, by designating a desired terminal of each functional block, it is possible to color-display wirings extending from the designated terminal and to individually confirm paths.

When the global wiring is completed, the operator performs individual route checks as described above as necessary (step S103). As a result, if room for improvement is found in the route (step S104; N),
This is corrected (step S105). If the route check at the global wiring level is OK by repeating the route check and the correction in this way (step S104;
Y) Then, detailed wiring is performed (step S106). In the detailed wiring step, detailed track assignment is performed for each wiring based on the wiring path determined by the global wiring. However, this allocation is performed only within one layer. That is, one wire is allowed to cross
Track assignment between individual terminals in the layer with individual conductors
It is. Therefore, at the time when the step of the detailed wiring is completed, there are a number of intersecting portions.

When the detailed wiring is completed, the check is performed next (step S107). The check in this case can also be performed by specifying individual wirings and displaying them in different colors in the same manner as described above. As a result of this wiring route check, if a route that has room for improvement is found (step S108; N), the route is corrected (step S109), and the route is checked again (step S107). As described above, when the route check at the detailed wiring level is completed by repeating the check and the correction, the process of the two-layer distribution is performed (step S1).
10).

The processing of the two-layer distribution is performed by, for example, a wiring method in an IC by the present applicant (Japanese Patent Laid-Open No. 3-142954).
The method may be performed as shown in FIG. By this two-layer distribution processing, the portion that crosses in one layer in the above detailed wiring step is distributed to two layers, and these crossing points are eliminated.

In this way, after a large number of wirings are distributed without crossing in the two layers, unnecessarily complicated parts are arranged, that is, compaction is performed (step S111).

As described above, in this embodiment, the global wiring and the detailed wiring are first performed only in one layer, and the result is subjected to the two-layer distribution. , And efficient wiring without waste can be performed.

FIG. 4 shows an enlarged display screen after detailed wiring of the area 14 surrounded by the dashed line in FIG. At this time, as shown in the figure, a crossing portion between a large number of wirings has occurred. FIG. 5 shows the result of performing two-layer distribution on such a detailed wiring result. As shown in this figure, the hatched wiring portions 18 and the like are distributed to the second layer, and the non-hatched wiring 17 and the like are distributed to the first layer. A via 15 or the like is provided at a connection point between the first layer and the second layer. As shown in this figure, conventional vertical and horizontal wirings are respectively connected to a first layer,
Unlike the method of distributing to the second layer, the vertical and horizontal wirings are arranged in one layer as a series as long as they do not hit an obstacle. Therefore, generation of unnecessary vias is suppressed as much as possible.

In this embodiment, the case of the two-layer wiring has been described. However, the present invention is not limited to this and can be applied to, for example, a multilayer wiring of more layers.

[0024]

As described above, according to the present invention,
Since the two-layer distribution process is made independent of the detailed wiring, it does not depend on the wiring order at all, and a wiring layout of almost constant quality can be obtained regardless of the experience of the person who performs the wiring. In addition, since the two-layer distribution process is independent, by appropriately setting the distribution algorithm, a layout that is conscious of circuit characteristics and a layout that sufficiently reflects the intention of the designer can be easily performed. Further, even if the correction is made manually, since the generation of useless vias and the like is already suppressed at the time when the two-layer distribution is completed as described above, the amount of correction is extremely small, and no labor is required.

Further, when there is a demand for arranging as many wirings as possible in one layer for reasons such as physical characteristics of each layer, it is possible to easily designate such a priority layer, which is ideal There is an effect that a multi-layer wiring can be realized.

In this embodiment, the wiring between each functional block or the input / output terminals has been described as an example. However, it is needless to say that the present invention can be applied to the wiring between gate elements in each functional block. .

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining a wiring method in an IC according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a state before wiring when the arrangement of functional blocks is completed.

FIG. 3 is an explanatory diagram showing a state where global wiring is completed.

FIG. 4 is a partially enlarged view showing a state at the time of completion of detailed wiring.

FIG. 5 is a partially enlarged view showing a state at the time when the two-layer distribution processing is completed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 I / O terminal 12 Function block 13 Display apparatus display screen 15 Via 17 1st layer wiring 18 2nd layer wiring

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-48071 (JP, A) JP-A-62-126467 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 658 H01L 21/82

Claims (3)

(57) [Claims] In an interactive design system for arranging elements in a semiconductor integrated circuit and performing multilayer wiring using a display device, in a first step, a connection path between terminals to be connected to each other is roughly set. In the second step, based on the connection path determined by the global wiring, a detailed wiring for wiring each terminal in a single layer between individual terminals is performed. A wiring method in an IC, wherein wiring is performed so that wirings formed in the detailed wiring step do not interfere with each other and are allocated to respective layers. 2. The wiring method in an IC according to claim 1, wherein
In the first step, a plurality of arrangements taking the same connection path are used.
Perform global wiring to determine the connection route by allowing
A wiring method in an IC. 3. The wiring method in an IC according to claim 1, wherein
In the second step, the crossing of wirings is allowed while
Track assignment between individual terminals in one layer with individual conductors
A wiring method in an IC, wherein a detailed wiring is performed.