JP2914025B2 - LSI automatic placement and routing processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic wiring processing method for an LSI by a computer, and more particularly to an automatic wiring processing method for reducing a wiring area by reducing a wiring length and reducing an LSI chip area.

[0002]

2. Description of the Related Art In a conventional method for processing the placement and routing of an LSI by a computer, as shown in FIG. 7, connection information (circuit diagram) between blocks, block shape information and the like are taken as input data 11, and a placement processing unit 12 is used. In the wiring processing unit 14a, the wiring processing unit 14a takes in the wiring area division designation input data 17 which is uniquely determined by the design rules such as the wiring width and the adjacent wiring distance and the like. A wiring route is determined by a wiring method such as a maze method using a grid-like small area formed by dividing in the horizontal direction.

[0003]

In this conventional placement and routing method, a grid-like region for searching for a wiring path is formed only in the vertical and horizontal directions, so that the wiring determined by the wiring process is vertical. It is obtained as a combination of line segments in the direction and the horizontal direction.

Here, as shown in FIG. 8, when terminals A and B are connected diagonally to a grid-like area for wiring route search, if the width of one grid is L, a straight line between the terminals is formed. While the distance is 5.6 L [4 × (square root of 2)], the shortest wiring length is 8 L in the conventional method.

As described above, in the prior art, since the method of dividing the area for searching the wiring route is inappropriate, it is not possible to obtain the wiring route with the shortest wiring length.

[0006] The object of the present invention is to eliminate such disadvantages.
An object of the present invention is to provide an automatic wiring processing method for an LSI that can obtain a shortest wiring length path.

[0007]

According to the structure of the present invention, an arrangement processing unit in an automatic placement and routing process of an LSI chip using a computer arranges logical blocks and performs wiring between the blocks. Vertical, water, and
In the automatic placement and routing processing method , placement is performed with reference to the xy axes that are flat axes, connection information between the blocks arranged by the placement processing unit is extracted, and automatic placement and routing is performed.
The wiring direction setting means determines a priority wiring direction that can be indicated by statistical means from the direction of the line segment connecting the corresponding blocks at the shortest distance, and determines the priority wiring direction and the x
First, using the wiring grid based on the y-axis,
Wiring is performed in the wiring direction.
Wiring grid based on the xy axis to avoid harm
The wiring processing unit determines a wiring path between the corresponding terminals according to the following .

[0008]

FIG. 1 is a block diagram showing the configuration of a system according to an embodiment of the present invention. In FIG. 1, a computer system 10 including a CPU, a memory, and the like is a system that performs an LSI arrangement and wiring process. Input data 11 of this system 10
Has information such as circuit connection information and block shape. The data format may be divided into a plurality of files, or may be a single file. The arrangement processing unit 12 arranges blocks based on the input data 11 using a known technique. The wiring direction setting unit 13 for searching for a wiring route executes a wiring direction setting process in this processing unit.

Here, each processing unit will be described in detail. FIG.
Is a detailed flowchart of the present embodiment, and steps 21 to 38 in the following description correspond to the processing steps shown in FIG.

First, in step 21, the process of reading circuit connection information from the input data 11 is started. Next, in step 22, a pair (hereinafter referred to as a terminal pair) is formed by the output terminal and the input terminal to be connected, and initial setting is performed.
Confirm that all terminal pairs have been registered.

In step 24, the terminal pairs are registered in the table while sequentially assigning numbers (step 25). The table referred to here is stored in a memory area inside the computer system in a form as shown as an example in FIG.

In this process, the terminal pair number 4 shown in FIG.
1 and names 42 and 43 of the output terminal and the input terminal of the terminal pair are stored. Here, since the normal wiring has a plurality of output terminals and input terminals, the correspondence is not limited to one-to-one, and each terminal may appear plural times. This processing exits the loop when all the terminals have been handled (YES in step 23).

Next, in steps 26 and 27, the placement processing unit 1
Input the processing result of 2. In the next step 28, all coordinates of each output terminal are searched, and the output terminal coordinates (An) in FIG.
Register at 44. Further, in step 29, all the coordinates of each input terminal are searched, and the input terminal coordinates (Bn) 45 in FIG.
(N + 1 → n: step 30) (n = I ?:
Step 31).

Based on the results of steps 28 and 29, vectorization in the wiring direction of each terminal pair is performed. The coordinates of the output terminal An are (a _xn , a _yn ), and the coordinates of the input terminal Bn are (b _xn , b
_yn ), the vector A _n B _n representing the wiring direction is represented by the following equation (1) as the absolute value of the difference between the respective coordinate values in order to make the vector component a positive value. 3
(Step 32)
~ 34).

[0015]

A vector sum is calculated for all terminal pairs,
The mean of all vectors obtained as the following equation (2), and registers to the vector _{A a} B _a 47 in FIG. 3 (step 35-3
7).

[0017]

Next, in step 38, the vector in the y-axis direction of the LSI chip is set as a vector C, and the vector in the x-axis direction is set as a vector D.

As a result of these processes, a wiring direction as exemplified in FIG. 4 is set. FIG. 4 shows information internally stored in the processing system, where 51 is a wiring area on an LSI chip assumed in the processing system, 52 is a vector sum A _{a Ba} , and 53 is an x-axis. The direction vector C, 54 is the y-axis direction vector D. When the processing of the wiring direction setting processing unit 13 is completed as described above, the wiring processing unit 14 is executed as follows.

From the output terminal A _n and the input terminal B _n , _a provisional line segment is generated in the direction of the vector A _a B _a , −vector A _a B _a .
If the tentative line segments are parallel and do not overlap, a tentative line segment is generated from one of the tentative line segments in the shorter direction in the vector C direction and the vector D direction in the two line segments. And intersect with the other temporary line segment. If the provisional line segment collides with an obstacle (location) such as a through hole or another block, the provisional line is moved in the direction of another set vector so as to avoid the obstacle (location). min continue to generate, a _n, to search the point where the temporary line segment is generated from each of the terminals of the B _n intersect, by tracing back from the resulting intersection configuration path connecting the a _n B _n Is done. Thus, the wiring route is determined, and the output result 15 is obtained.

FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention. In the present embodiment, the wiring region on the LSI is divided into a plurality of regions by the division processing unit 16, and wiring processing is performed for each of the regions. A wiring direction setting unit 13a for searching for a wiring route is applied to each region. To determine the optimal wiring direction.

FIG. 6 is a diagram exemplifying information internally stored in the wiring processing system of the embodiment of FIG. This embodiment is different from the first embodiment in that the wiring area is composed of four wiring areas 61.
The wiring direction is set for each of these regions, and local variations in the wiring direction are reflected in more detail than in the first embodiment. That is, the vector sums 65 to 68 are set for the respective x-axis vectors and y-axis vectors 69 and 70 corresponding to the first to fourth wiring regions 61 to 64, respectively.

[0023]

As described above, the present invention has an effect that the optimum wiring direction can be obtained because the wiring direction setting means for searching the wiring path sets the optimum wiring direction.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system according to an embodiment of the present invention.

FIG. 2 is a detailed flowchart of one embodiment of the present invention.

FIG. 3 is a sectional view of a memory area of the computerized system according to the embodiment of FIG. 1;

FIG. 4 is a schematic diagram showing an example of internal information of the system of FIG. 1;

FIG. 5 is a block diagram of a system according to a second embodiment of the present invention.

FIG. 6 is a vector diagram of an example of internal information of the wiring processing system of FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional wiring processing system.

FIG. 8 is a vector diagram of an example of a wiring area according to the system of FIG. 7;

[Explanation of symbols]

 10, 10a computer system 11 input data 12 placement processing unit 13 wiring direction setting processing unit 14, 14a wiring processing unit 15 output result 16 division processing unit 17 input data for wiring area division designation 21 to 38 processing step 41 terminal pair number 42 output Terminal name 43 Input terminal name 44 Output terminal coordinates 45 Input terminal coordinates 46 Wiring direction vector 47, 52 Wiring direction vector sum 51 Wiring area 53, 69 Y-axis direction vector 54, 70 X-axis direction vector 61-64 Division area 65-68 Wiring direction vector sum for each area

Claims (1)

(57) [Claims] An arrangement processing unit in an automatic placement and routing process for an LSI chip using a computer arranges logical blocks, performs wiring between the blocks, and performs connection information between the blocks and the shape of the blocks. Automatic placement is performed based on the xy axes that are the vertical and horizontal axes using the placement condition as a reference, and connection information between the blocks arranged by the placement processing unit is extracted to perform automatic placement and routing.
In the wiring processing method, it is possible to indicate by statistical means from the direction of the line segment connecting the corresponding blocks at the shortest distance.
The priority wiring direction determined by the wiring direction setting means, said Yu
Combined use of the leading wiring direction and the wiring grid based on the xy axis
First, wire in the priority wiring direction, and
The xy axis so as to avoid a failure point where wiring cannot be
An automatic placement and routing processing method, wherein a routing path between the corresponding terminals is determined by the routing unit according to a reference wiring grid .