JP2566788B2 - Printed circuit board wiring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The wiring system of a printed circuit board is optimized by minimizing the crossing in the entire system of the printed circuit board while performing a relative crossing evaluation between the lands on which the parts are arranged. With respect to the above, it is an object of the present invention to provide a wiring method for a printed circuit board that can shorten the wiring length as much as possible without causing unnecessary vias and the situation of non-wiring. For each of the plurality of connecting point series in the block area created by the above, a row of polygonal areas including between two points to be connected is created, and (b) the polygonal area in the entire printed board or the block area is created. The number of intersections and the number of intersections are obtained by examining the intersection state of (c), and the sum of the number of intersections is the smallest among the plurality of intersection region rows from one of the two points to be connected to the other. Become The configuration requirement is that the intersection region row is obtained and the intersection region row is used as an area path for connecting two points.

[Industrial applications]

The present invention relates to a printed circuit board wiring system that optimizes the connection between lands on which components are arranged by minimizing the crossover in the entire system of the printed circuit board while performing relative crossover evaluation.

[Conventional technology]

Conventional automatic wiring processing methods are self-type or event-type. The self-type is a method for performing wiring processing without considering other areas and connection systems, and the event type is a method for performing wiring without considering later such as an occupied area after wiring.

[Problems to be solved by the invention]

Since the conventional automatic wiring method is self-typed or event-typed, the correlation degree due to other relationships is not grasped, so that the dependence on the wiring order is large, and the unrouted area within the area depends on the wiring route within the wiring area. Is a large factor. In particular, as the wiring density in the area becomes higher, it is necessary to perform wiring in consideration of mutual area occupancy of the connection system, and since the above is not taken into consideration in the conventional method, the probability of unwiring is high. The cause of the non-wiring is caused by the generation of useless vias (ViA) and the shape of the wiring path in the area (effective wiring area) mutually hinders the wiring path.

The present invention was created in view of this point,
Without causing useless vias and unwired situations,
It is an object of the present invention to provide a printed circuit board wiring system in which the wiring length can be made as short as possible.

[Means for solving problems]

FIG. 1 is a principle diagram of the present invention. The wiring method of the printed board of the present invention is (a) a polygon including two points to be connected to each of a plurality of connecting point series in the entire printed board or a block area created by dividing the printed board. Create a row of areas, and (b) find the intersection area and the number of intersections by examining the intersection status of the polygonal areas in the entire printed board or block area. (C) From one of the two points to be connected The configuration requirement is to find the intersection region row having the smallest sum of the number of intersections from the plurality of intersection region rows leading to the other point, and to set the intersection region row as the region path for connecting the two points. .

〔Example〕

FIG. 2 is a diagram for explaining the area division of the printed board.
The printed board is divided into a plurality of block areas according to functions, such as a microprocessor section, a memory circuit section, an LSI section, and a driver circuit section.

FIG. 3 is a diagram showing an example of intersection areas and the number of intersections in the block area. In the figure, a small circle indicates a land, and a dotted line indicates a wiring between two lands to be connected. A rectangle with a diagonal line connecting the lands LA1 and LA2 is A
B indicates a rectangle having a diagonal line connecting the lands LB1 and LB2. Hereinafter, it is as illustrated. Land LA
The wiring connecting 1 and LA2 is performed so that the wiring path exists in the rectangular area A. The Arabic numerals written in the block area of FIG. 3 represent the number of intersections. For example, the rectangle A overlaps the rectangle C, the rectangle D, and the rectangle E. The number indicating the depth of superposition is called the number of intersections.

FIG. 4 is a diagram for explaining how to obtain a wiring path connecting the lands LA1 and LA2. FIG. 4A shows the number of intersections and the number of intersections in the shortest rectangular area A. Area A-
The number of intersections of 1 is 1, the number of intersections of the region A-2 is 2, the number of intersections of the region A-3 is 3, the number of intersections of the region A-4 is 3, and the number of intersections of the region A-5 is 3. The number of intersections is 3, and area A
The number of intersections at −6 is 2, and the number of intersections at the region A-7 is 3.

In the shortest rectangular area A, the sum of the number of intersections in the intersection area row including the wirable path from the lands LA1 to LA2 therein is obtained. For example, A-1 → A-6 →
The sum of the number of intersections in the intersection region sequence of A-7 is 1 + 2 + 3 = 6, and the sum of the number of intersections in the intersection region sequence of A-1 → A-2 → A-5 → A-7 is 1 + 2 + 3 + 3 = 9, A-1 → A-2
The sum of the number of intersections in the intersection region sequence of → A-3 → A-4 → A-7 is 1 + 2 + 3 + 3 + 3 = 12. Among the intersection area rows including the wirable path from the land LA1 to the land LA2, the intersection area row having the smallest sum of the number of intersections is A-1 → A-6 → A−.
7 is a row of intersection regions.

A'in FIG. 4 (b) shows an area formed by the intersection areas A-1, A-6, A-7. The wiring pattern that connects the sections of the lands LA1 and LA2 is shaped so as to exist in the area A '. A region in which a wiring pattern for connecting two points is permitted is called a region path. When there are a plurality of intersecting region columns having the smallest sum of the number of intersecting regions, the one having the smallest area is selected. FIG. 4 (c) shows an example of wiring pattern candidates. This wiring pattern surrounds the upper side of the area A ', but a plurality of wiring patterns are prepared in a table other than the one shown in the figure.

For rectangular areas B, C, ... in the block area,
The same processing as that performed on the rectangular area A is performed. After obtaining wiring pattern candidates for all rectangular areas A, B, C, ..., Wiring of the block area is performed using these wiring patterns.

FIG. 5 is a diagram showing an example of a row of rectangular areas corresponding to a row of connection points. In the figure, the lands connected by the dotted lines have the same potential. Columns A1, A2, ..., A6 of rectangular areas are created corresponding to the series L1, L2, ..., L7 of connection points. The rectangular area A1 is a rectangle having a line segment connecting the lands L1 and L2 as a diagonal line, and the rectangular area A2 is a rectangle having a line segment connecting the lands L2 and L3 as a diagonal line. Hereinafter, it is as illustrated. Columns of rectangular area A1, A2,
The wiring is designed so that the wiring path connecting the lands L1, L2, ..., L7 exists in A6.

 FIG. 6 is a diagram showing the flow of the wiring process of the present invention.

Step 10: The printed board is divided by function, for example, the MPU circuit section, the memory circuit section, the LSI circuit section, and the driver circuit section, and area division is performed for each function constituting the circuit as a unit.

Step 20: With respect to the block area divided by the processing shown in step 10, the shortest path of the connected systems included in the block area is arithmetically processed, and the shortest polygon decomposition that connects those systems is temporarily performed. Treat as a path.

Step 30: Create a column of the shortest rectangular area including one side of the shortest polygon constituted by the temporary path determined in Step 20.

Step 40: The process of step 30 is similarly performed on the other systems to be connected created in step 10.

Step 50: Calculate and evaluate the mutual intersection area and the number of intersections in the column of the shortest rectangular area generated in step 30 or step 40.

Step 60: Regarding the shortest rectangular area, a plurality of intersecting area columns that may include a wiring path connecting two points are obtained, and the sum of the number of intersections in each intersecting area column is calculated.

Step 70: It is checked whether or not there is a crossing region sequence in which the sum of the crossing numbers is the same. If there is an intersection region column having the same number of intersections, the intersection region column having the smaller area is prioritized as shown in step 110.

Step 80: In the shortest rectangular area, the area formed by the intersection area row having the smallest sum of the number of intersections is selected as the area path.

Step 90: By the processing of step 80, the intersection area row (area path) in which the sum of the number of intersections is minimized is determined. In order to determine the actual wiring path, the outer shape path surrounding the area path is set as the priority path. Also, the deformation path is determined within the area path.

Step 100: Determine an automatic wiring path that minimizes intersections. Through the above process, the route determination process of the automatic wiring process for minimizing the intersection by the virtual route and thereby optimizing the region is performed.

FIG. 7 is a diagram showing another example of a rectangular area sequence for a connection point series. Find the center of gravity of the series L1, L2, ..., L8 of connection points.
A line parallel to the X axis passing through the center of gravity is drawn, and this line is used as the backbone line. Draw a perpendicular line from each connection point L1, L2, ... L8 to the backbone line. For example, the intersection of the vertical line and the trunk line drawn from the connection point L1 is P3, and the intersection of the vertical line and the trunk line drawn from the connection point L2 is P6. The rectangle composed of points P3, P6, L2, C1 is A1, and the rectangle composed of points P6, P7, C2, L2 is A2.
And Similarly, rectangles A3, A4, ..., A8 are created. The rectangular area sequence for the connection point series L1, L2, ..., L8 is A1, A2 ,.
It will be A8.

FIG. 8 is a diagram showing another example of a region surrounding two points to be connected. As shown in FIG. 8, a region surrounding two points to be connected may be a parallelogram having a line segment connecting a start point and an end point as a diagonal line. The diagonal line segment of the parallelogram is, for example, 45 degrees. In FIG. 8, such parallelogram areas and rectangular areas are mixed.

In the explanation related to FIG. 2, the printed board is divided into functional units, but the basic number of divisions is determined and simple division (for example, the total area of the printed board is divided into 20 equal parts, and the polygon is formed at the place where the parts are separated well). Area). In addition, the total effective wiring area is calculated for all printed boards, and in the connection relationship between the parts arranged, the shortest path is used as the temporary path and the area occupancy rate is grasped for each vertical or horizontal component. You may divide into blocks so that they may be equalized.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, (a) the path inference and the path determination can be performed while evaluating the relative area intersection in the entire printed board or in the divided block areas.

(B) Free prediction that does not depend on ordering becomes possible,
Useless via does not occur. Therefore, the via can be optimized.

(C) The automatic wiring rate of high-density wiring processing in the printed board or block area is improved.

(D) It is effective for layer division of automatic wiring processing for mounting surface mount components.

(E) Effective for automatic wiring processing of LSI and VLSI.

And so on.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a diagram showing the area division of a printed board, FIG. 3 is a diagram showing an example of an intersection region and the number of intersections in a block region, and FIG. 4 is a land LA1 and a land LA2. FIG. 5 is a diagram for explaining a method of obtaining a wiring path connecting the lines, FIG. 5 is a diagram showing an example of a rectangular area sequence for a connection point series, FIG. 6 is a diagram showing an example of a wiring process flow of the present invention, FIG. 7 is a diagram showing another example of a rectangular region sequence for a connection point series, and FIG. 8 is a diagram showing another example of a region surrounding two points to be connected.

Claims (1)

(57) [Claims] (A) For each of a plurality of connecting point series in a block area formed by dividing the entire printed board or the printed board, a row of polygonal areas including two points to be connected is created. Then, (b) the intersection area and the number of intersections are obtained by examining the intersection state of the polygonal area in the entire printed board or the block area, and (c) from one of the two points to be connected to the other point. A wiring system for a printed circuit board, wherein an intersection area row having the smallest sum of the number of intersections is obtained from the plurality of intersection area rows and the intersection area row is used as an area path for connecting two points.