JP2682219B2 - Wiring method for semiconductor integrated circuit - Google Patents

Description

The present invention relates to a wiring method for a semiconductor integrated circuit, and more particularly to a wiring method for a semiconductor integrated circuit performed by computer aided design.

[Conventional technology]

In computer-aided design of semiconductor integrated circuits, generally, circuit blocks of a semiconductor integrated circuit including a plurality of circuit blocks are connected by vertical and horizontal bidirectional wirings.

In this case, by providing the wiring paths on the circuit blocks, the number of wirings between the circuit blocks can be reduced, and therefore the distance between the circuit blocks can be reduced, and as a result, the degree of integration can be improved.

As shown in FIG. 3, the conventional wiring method of this kind of semiconductor integrated circuit is such that a plurality of wirings having a minimum space for wiring, that is, one wiring space, is provided at a position usable as a wiring path on the circuit block 1. The wiring route pattern 3 is generated, an arbitrary wiring route is selected from the wiring route pattern 3, and the on-block wiring 4 from the terminal 5 is performed.

[Problems to be solved by the invention]

In the conventional wiring method for a semiconductor integrated circuit described above, a pass candidate line extending from a terminal connecting the line to the direction of a circuit block through which the line passes and a wiring route on the circuit block through which the pass candidate line passes If they do not match, there is a drawback that the interval between the passing candidate line and the wiring route often becomes within one wiring interval that cannot be used for preventing a short circuit.

Therefore, since a repair process such as bypassing the wiring or changing to another terminal is required, the distance between the wirings increases, and therefore the space between the circuit blocks also increases and the packaging density decreases. there were.

[Means for solving the problem]

A wiring method for a semiconductor integrated circuit according to the present invention is a wiring method for a semiconductor integrated circuit, wherein terminals of a plurality of circuit blocks forming an integrated circuit are connected by bidirectional wiring in vertical and horizontal directions. Set a plurality of wiring route candidates for each wiring interval of a predetermined unit interval of a predetermined wiring layer that allows the wiring to pass, and extend from the terminal to which the wiring is connected in the direction of the circuit block through which the wiring passes. If the passing candidate line and the position of the candidate of the wiring route on the circuit block through which the passing candidate line passes do not match, the gap between the passing candidate line and the candidate of the wiring route is the wiring. It is characterized in that the wiring paths having a distance equal to or less than the interval are excluded from designation of the wiring path candidates.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a wiring path of a semiconductor integrated circuit for explaining an embodiment of the present invention.

In FIG. 1, a circuit block 1 to which wiring is connected
And the circuit block 2 through which the wiring passes and each circuit block
A plurality of wiring route patterns 3 set at predetermined wiring intervals P on the wirings 1, 2; on-block wiring 4 passing through the selected wiring route; and a terminal 5 to which the wiring of the circuit block 1 is connected, A wiring 6 from the terminal 5 to the circuit block 2 and a wiring route pattern within one wiring interval P from an extension line from the terminal 5 to the circuit block 2, that is, a non-adopted wiring route pattern 7 are shown.

Next, the flow of the wiring method according to this embodiment will be described.

FIG. 2 is a flowchart of the wiring method of this embodiment shown in FIG.

In FIG. 2, first, the terminal 5 to which the wiring of the circuit block 1 of FIG. 1 is connected is set (step R1).

Next, from the wiring route pattern 3 on the circuit block 2 through which the wiring passes, an arbitrary wiring route for passing the on-block wiring 4 is selected (step R2).

Next, it is judged whether or not the extension line from the terminal 5 and the selected wiring route match (step R2).

If YES, the process proceeds to step R5 and the wiring is performed by the straight inter-block wiring 6.

If no, the process proceeds to step R4, and it is determined whether or not the interval between the extension line from the terminal 5 and the selected wiring path is less than or equal to one wiring interval P.

If the answer is yes, this wiring route is the rejected wiring route pattern 7, and therefore the process returns to step R2 to reselect the wiring route.

If NO, the process proceeds to step R5 and the inter-block wiring 6 is used as it is.

The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments, and various modifications can be made.

〔The invention's effect〕

As described above, according to the present invention, when wiring between circuit blocks of a semiconductor integrated circuit is performed via a wiring route set on the circuit block, the circuit block through which the wiring passes from a terminal connecting the wiring. When the line extended in the direction of and the wiring route on the circuit block through which the wiring passes do not match, the wiring route is bypassed by excluding the wiring route candidates whose gap is within the unit wiring interval. Also, there is an effect that a relief process such as changing to another terminal becomes unnecessary.

Therefore, it is not necessary to increase the wiring interval,
As a result, the distance between the circuit blocks can be reduced, and the packaging density can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a wiring route for explaining an embodiment of the present invention, FIG. 2 is a flowchart of a wiring method of the present embodiment shown in FIG. 1, and FIG. 3 is a wiring of a conventional semiconductor integrated circuit. It is a figure which shows the wiring path for demonstrating a method. 1,2 ... Circuit block, 3 ... Wiring route pattern, 4 ...
... Wiring on block, 5 ... Terminal, 6 ... Wiring, 7 ... Not adopted wiring route pattern.

Claims (2)

(57) [Claims] 1. A wiring method for a semiconductor integrated circuit in which terminals of a plurality of circuit blocks constituting an integrated circuit are connected by wirings in two directions, vertical and horizontal, wherein a wiring is passed over the circuit block. A plurality of wiring route candidates for each wiring interval of a predetermined unit interval between the wirings, and a passing candidate line extended in the direction of the circuit block through which the wiring passes from the terminal to which the wiring is connected. The wiring in which the crossover distance between the candidate wiring line and the candidate wiring path is equal to or less than the wiring distance when the position of the candidate wiring path on the circuit block through which the candidate wiring line passes does not match. A wiring method for a semiconductor integrated circuit, wherein a route is excluded by designating a candidate of the wiring route. 2. A step of setting a candidate for the wiring path on the circuit block, a step of selecting the wiring path, and a passing candidate line extending in the direction of the circuit block through which the wiring passes from the terminal. Determining a match with the position of the wiring route candidate on the circuit block through which the wiring passes, and a crossing interval between the passing candidate line and the wiring route candidate in the case of the mismatch is the wiring interval. The method according to claim 1, further comprising a step of determining whether or not the wiring path is below, and a step of excluding the wiring path from designation of a candidate of the wiring path when the crossing distance is equal to or less than the wiring distance. Wiring method for semiconductor integrated circuit.