JP2972713B2 - Semiconductor integrated circuit manufacturing apparatus, semiconductor integrated circuit wiring method, and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit.
More specifically, the present invention relates to an ASIC (Application), a wiring method for a semiconductor integrated circuit, and a recording medium.
Speci? C integrated circuit
It is suitable for use in automatic wiring processing of a semiconductor integrated circuit that performs layout processing by automatic placement and wiring represented by t).
The present invention relates to a semiconductor integrated circuit manufacturing apparatus, a wiring method for a semiconductor integrated circuit, and a recording medium.

[0002]

2. Description of the Related Art For example, in an automatic wiring process of a semiconductor integrated circuit in which a layout process is performed by automatic placement and routing represented by an ASIC, generally, the wiring length of wiring aluminum varies, so that the wiring load capacity of the semiconductor is reduced. Affects propagation delay characteristics. The length of wiring is an important factor in the timing design of circuits. In recent years, as fine processing has progressed and the degree of integration of semiconductors has improved, the wiring load capacitance due to wiring aluminum has a dominant influence on the propagation delay characteristics of semiconductors. Because of the influence, it is required to control the length of the wiring aluminum in a critical signal propagation path.

In order to meet this demand, for example, as disclosed in Japanese Patent Application No. 3-173471, a wiring layer in which vertical and horizontal wiring grids are defined and a wiring grid connecting diagonal lines of both grids are formed. It has been proposed that by providing a defined wiring layer, the wiring length can be adjusted relatively easily.

[0004]

[Problems to be Solved by the Invention] The above-mentioned Japanese Patent Application No. 3-173.
Although the method disclosed in FIG. 471 is shown in FIG. 4, as will be apparent from a comparison of FIG. 1 showing a wiring example according to an embodiment of the present invention described later, vertical and horizontal wiring grids are provided. Therefore, there is no absolute equidistant property with respect to a specific positional relationship due to the restriction of the geometrical figure of the wiring grid.

[0005] For this reason, in the wiring processing at the time of automatic wiring, for example, when wiring is performed from a certain point to two points on a straight line on a wiring grid slightly apart from one point, one of the two points on the straight line is used. Is located at the same position as the vertical or horizontal coordinate of a point, the wiring connecting the two points on the straight line and the point is
When connecting at the shortest distance, there is a problem that connection is always made with a different wiring length.

As a result, since the lengths of the respective wirings are different, the magnitude of the wiring load capacitance in each path is different, and there is a problem that the characteristics of the propagation delay cannot be made the same.

Furthermore, since there are many combinations of wiring routes that can be selected, the algorithm for automatic wiring becomes complicated, and there is a problem that the processing time of the automatic wiring processing increases.

[0008] The present invention has been made in view of such circumstances, and if the positional relationship under specific conditions,
It is possible to provide a wiring method for a semiconductor integrated circuit in which a wiring at the shortest distance connecting two points is always connected with the same wiring length, and a processing for checking specific conditions is provided as a wiring processing flow. Is to do so.

[0009]

According to a first aspect of the present invention, there is provided a wiring method for a semiconductor integrated circuit, wherein wiring is performed using a wiring grid including a first layer wiring and a second layer wiring which cross each other. The third point so that the positional relationship between the first point and the second and third points, each of which is wired at the shortest distance, satisfies a predetermined constraint based on the geometric shape.
And a wiring path determining step of determining each wiring path between the first point and the second point, and between the first point and the third point. In the determining step, the third point has the first point as the vertex, passes through the second point, and connects the diagonals of the wiring grid including the second point.
Includes a second point among sides of the triangle formed by the three straight lines, the first wiring passing through the first point, and the second wiring passing through the first point, excluding the first point. The third point is located on the side, and the position of the third point is determined so that the wiring length of each wiring path is the same. The semiconductor according to claim 2.
The semiconductor integrated circuit manufacturing apparatus includes a semiconductor device that performs wiring using a wiring grid including a first wiring and a second wiring that cross each other.
The apparatus for manufacturing a body integrated circuit, wherein a positional relationship between a first point and second and third points each wired at the shortest distance satisfies a predetermined constraint based on a geometric shape. Position determination means for determining the position of the third point, and path determination means for determining each wiring path between the first point and the second point and between the first point and the third point. By the determining means, the third point passes through the first point, the two straight lines passing through the second point, connecting the diagonal of the wiring grid including the second point, and the first point. Among the sides not including the first point of the triangle formed by the first wiring and the second wiring passing through the first point, the third point is arranged on the side including the second point. Is determined so that the wiring length of each wiring path is the same. According to a third aspect of the present invention, there is provided a recording medium on which a program capable of executing the wiring method for a semiconductor integrated circuit according to the first aspect is recorded. Semiconductor according to the present invention
Body integrated circuit manufacturing apparatus and semiconductor integrated circuit wiring method,
In the recording medium, the third point is set such that the positional relationship between the first point and the second and third points, each of which is wired at the shortest distance, satisfies a predetermined constraint based on the geometric shape. Are determined, and the first point and the second point, and the first point and the third point are determined.
Each wiring route between the points is determined. At this time, the third point has the first point as the vertex, passes through the second point, and
A first point of a triangle constituted by two straight lines connecting the diagonals of the wiring grid including the points (1), (2), a first line passing through the first point, and a second line passing through the first point. Of the sides not included,
The third point is located on the side including the second point, and the position of the third point is determined such that the wiring lengths of the respective wiring paths are the same.

[0010]

FIG. 1 shows a wiring grid structure in a wiring method of a semiconductor integrated circuit according to the present invention. In contrast to the conventional configuration in which a wiring layer in which vertical and horizontal wiring grids are defined and a wiring layer in which a wiring grid connecting diagonals of both grids are provided, the semiconductor integrated circuit of the present invention shown in FIG. In the case of the wiring grid structure in the wiring method, a wiring layer in which a wiring grid formed by oblique lines is defined is provided, and as shown in the flowchart of the automatic wiring processing in FIG. The automatic routing process is performed on the shortest distance wiring route after confirming that the constraints due to various shapes are satisfied.

The processing of confirming the positional relationship between the wiring grid structure and the two points to be connected, as shown in the flowchart of FIG. 3, and performing automatic wiring on the shortest wiring path is performed by two sets of the same starting point. Two points must be connected with the same wiring length. Accordingly, it is possible to eliminate the variation in the wiring length of the wiring aluminum in the automatic wiring processing, and to obtain the effect that the characteristics of the propagation delay due to the wiring load capacitance become the same.

FIG. 1 shows the structure of a wiring grid. The wiring grid is composed of two wiring layers formed by diagonal lines, and the diagonal lines are formed by a first wiring layer 1 and a second wiring layer 2 defined by diagonal lines crossing the first wiring layer.

Symbols for explaining the operation include intersections P1, Pn, Pn + 1, P2, P3, P2a, P3a,
Straight lines L1, L1a, L2, L3 and line segments dL, dLa
It is shown.

FIG. 2 is a circuit diagram corresponding to the operation of FIG. This circuit diagram shows three blocks B1, B
2 and B3, and it is assumed that the same length of the wiring L12 and the wiring L13 is required as a characteristic.

FIG. 3 is a flowchart showing a method for wiring a semiconductor integrated circuit according to the present invention. This flowchart is
In addition to the conventional automatic wiring processing, the present invention has a processing of confirming a positional relationship between two connected points based on a constraint of a geometrical figure according to the present invention, and rearranging blocks as necessary.
It should be noted that the automatic arrangement processing, block rearrangement processing, and automatic wiring processing of FIG. 3 are well known to those skilled in the art and are not directly related to the present invention. Omitted.

The operation of the above embodiment will be described below. First, restrictions on geometric figures will be described with reference to a wiring grid diagram of FIG. 1 showing a wiring grid structure.

First, an intersection P1 on a wiring grid at an interval d consisting of oblique lines 1 and 2; an arbitrary straight line L1 connecting diagonals of the wiring grid not including the intersection P1; and a wiring grid passing through the intersection P1. Two straight lines L2 and L3 are defined. Next, the intersection of the straight line L1 and the straight line L2 is P2, and the intersection of the straight line L1 and the straight line L3 is P3. Then, a line segment on the straight line L1 separated by the intersection point P2 and the intersection point P3 is defined as a line segment dL.

Here, consider wiring from the intersection P1 on the wiring grid to any of the intersections Pn and Pn + 1 of the wiring grid on the line segment dL on the straight line L1 including the intersections P2 and P3.
It can be seen that when the wiring is on the wiring grid and the shortest distance wiring is performed, the wiring length is always 8d regardless of which route is followed.

Next, the correspondence between the semiconductor circuit and the wiring grid will be described with reference to the wiring grid diagram of FIG. 1 and the semiconductor circuit diagram of FIG. As shown in FIG. 2, three blocks B1, B
2, B3, connection point N1 of block B1, block B2
, A connection point N3 of the block B3, a wiring L12 from the connection point N1 to the connection point N2, and a wiring L13 from the connection point N1 to the connection point N3.
The connection point N1 is arranged at the position of the intersection P1 in FIG.
The connection point N2 is arranged at the position of the intersection Pn in FIG.
The connection point N3 corresponds to the intersection Pn + 1 in FIG.
Shall be arranged at the position of. At this time, as described above, when the wiring L12 is wired with the shortest distance, the wiring length 8d
If the wiring L13 is also wired at the shortest distance, it is wired with a wiring length of 8d, so that a wiring in which the wiring length of the wiring L12 and the wiring length of the wiring L13 are equal (L12 = L13) is realized.

Finally, a wiring method incorporating the above-described restrictions will be described with reference to the flowchart of FIG. 3 using the wiring grid diagram of FIG. 1 and the circuit diagram of FIG. As shown in FIG. 3, after the conventional automatic arrangement processing is completed, the intersection P1 of FIG. 1 which is the connection point N1 of the block B1 of FIG. 2 and the intersection of FIG. 1 which is the connection point N2 of the block B2 of FIG. Find the position of Pn. When the position of the intersection Pn is determined, two straight lines L1 and L1a passing through the intersection Pn and connecting the diagonals of the wiring grid are obtained.
Is obtained.

In each of the straight line L1 and the straight line L1a, the positions of the intersection points P2 and P3 and the intersection points P2a and P3a are obtained, and a line segment dL separated by the intersection point P2 and the intersection point P3;
A line segment dLa delimited by the intersection P2a and the intersection P3a is obtained. Thereafter, a line segment including the intersection Pn (the line segment d in FIG. 1)
L). Subsequently, the connection point N of the block B3 in FIG.
The position of the intersection Pn + 1, which is 3, is determined, and it is checked whether the intersection Pn + 1 exists on the line segment dL. as a result,
When it is determined that the intersection Pn + 1 does not exist on the line segment dL, the block B3 in FIG. 2 is rearranged again, and it is checked again whether the intersection Pn + 1 exists on the line segment dL. Then, this processing is repeated until the intersection Pn + 1 comes on the line segment dL.

When the intersection points P1, Pn, and Pn + 1 are arranged in a predetermined positional relationship such that the intersection point Pn + 1 exists on the line segment dL, the shortest path on the wiring grid between the intersection point P1 and the intersection point Pn is determined. The shortest paths on the wiring grid between the intersections Pn + 1 are respectively obtained, and based on the route information, the intersections between the intersections, that is, the intersections P1 and P
n, and the intersection P1 and the intersection Pn + 1 are respectively wired.

As described above, the wiring grid is constituted by the wiring layers formed by diagonal lines, and it is confirmed whether or not the positional relationship between the two points to be connected satisfies the restriction by the geometrical shape. By connecting the wiring paths in such a manner, the wiring length can always be the same for two sets of two points having the same starting point. Therefore,
Variations in the wiring length of the wiring aluminum in automatic wiring processing can be eliminated. As a result, the effect that the characteristics of the propagation delay due to the wiring load become the same can be obtained.

Further, all the wiring routes connected at the shortest distance have the same wiring length, and the condition for determining the wiring route is only the shortest distance route designation. For this reason, the processing for obtaining the wiring route is also simplified, and the TAT (tur
n-around time (delivery time) can be shortened.

In the above-described embodiment, a description has been given of the case of a connection between two points where two sets of starting points are the same. However, a case of a connection between two points where the starting points of three or more sets are the same is also described. The present invention can be applied.

[0026]

According to the semiconductor integrated circuit manufacturing apparatus, the semiconductor integrated circuit wiring method, and the recording medium according to the present invention, the second and third wirings are wired at the shortest distance from the first point.
The position of the third point is determined such that the positional relationship between the points satisfies a predetermined constraint based on the geometric shape, and the first point and the second point, and the first point and the Each wiring route to the third point is determined. At this time, the third point has the first point as the vertex, passes through the second point, and connects two straight lines connecting the diagonals of the wiring grid including the second point, and the third point passing through the first point. 1 wiring,
Of the sides not including the first point of the triangle formed by the second wiring passing through the first point, the triangles are arranged on the side including the second point, and the position of the third point is determined by each wiring. Since the wiring lengths of the routes are determined so as to be the same, the connection between the two points having the same starting point can be performed with the same wiring length, and the wiring load of each wiring route depends on the wiring load. The characteristics of the propagation delay can be made the same.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a wiring grid used in a semiconductor integrated circuit manufacturing apparatus of the present invention.

FIG. 2 is a diagram showing a circuit corresponding to the connection of the wiring grid in FIG.

FIG. 3 is a flowchart showing a procedure for performing the wiring processing of FIG. 1;

FIG. 4 is a diagram showing a structure of a conventional wiring grid and wiring paths.

[Explanation of symbols]

 1, 2 wiring layers 11, 12 wiring layers

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/82 G06F 17/50

Claims (3)

(57) [Claims] 1. A wiring method for a semiconductor integrated circuit, wherein wiring is performed by using a wiring grid composed of a first layer wiring and a second layer wiring crossing each other, wherein a second wiring is provided at a shortest distance from the first point. And a position determining step of determining the position of the third point so that the positional relationship between the third point and the third point satisfies a predetermined constraint based on a geometrical shape. Point 2, the first point and the third point.
A wiring path determining step of determining each wiring path between the second point and the third point, wherein the third point has the first point as a vertex, passes through the second point, And two straight lines connecting diagonals of a wiring grid including the second point, the first wiring passing through the first point, and the second wiring passing through the first point. Among the sides of the triangle not including the first point, the sides of the triangle including the second point are determined, and the position of the third point is determined so that the wiring length of each wiring path is the same. A wiring method for a semiconductor integrated circuit. 2. A semiconductor integrated circuit for performing wiring using a wiring grid composed of a first wiring and a second wiring crossing each other.
A road manufacturing apparatus , wherein the positional relationship between a first point and second and third points, each of which is wired with the shortest distance, satisfies a predetermined constraint based on a geometric shape. Position determining means for determining the position of the first point, the first point and the second point, and the first point and the third point.
Route determination means for determining each wiring route between the third point and the third point, the third point having the first point as a vertex, passing through the second point, and It is composed of two straight lines connecting diagonals of a wiring grid including the second point, the first wiring passing through the first point, and the second wiring passing through the first point. Of the sides of the triangle not including the first point, the triangles are arranged on the side including the second point,
The position of the third point is determined so that the wiring length of each wiring path is the same .
Manufacturing equipment . 3. A recording medium on which a program capable of executing the wiring method for a semiconductor integrated circuit according to claim 1 is recorded.