JP3184132B2 - Hierarchical layout design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical layout design method, and more particularly, to a hierarchical layout design method for shortening wiring length by laying a buffer for connecting the uppermost hierarchical wiring and a region for the uppermost hierarchical wiring.

[0002]

2. Description of the Related Art FIG. 6 is a schematic diagram showing a conventional macroblock. Conventionally, for the redundant wiring D2 at the highest hierarchical level that passes over a macroblock, the wiring length is shortened or corrected, or a buffer block D3 is arranged around the macroblock and additionally connected to reduce the wiring length. Shorten it or
Alternatively, a buffer block D3 is additionally arranged by using an arrangement wiring gap in a hierarchical macro block as an arrangement area for the highest hierarchy, thereby reducing the wiring length. With respect to the initial redundant wiring D2 shown in (J),
By adding a buffer block D3 around the macro block (arrow H) and shortening the wiring length as shown in (K),
With respect to the redundant wiring D2 of (J), a buffer block is added to the arrangement wiring gap area without a macroblock (arrow I), and a buffer block D3 is added as shown in (L). D4 is a block already arranged in the macroblock, and D5 is a wiring already arranged in the macroblock.

[0003]

In the above-mentioned conventional example,
When there are a plurality of large-scale macroblocks or when the used block density is high, it is not possible to secure a sufficient area for moving the preceding and succeeding blocks, so that it is difficult to shorten the wiring length. Also, when the wiring density is high, even if the bypassed redundant wiring is shortened and corrected, a sufficient wiring area cannot be secured, so that it is difficult to shorten the wiring length. Therefore, there is a problem that it may be difficult to shorten the redundant wiring passing over the macroblock by manual correction.

Further, even if a buffer block is additionally arranged around a macro block and connected to a pass-through line above the macro block, the buffer block cannot be reduced to a width equal to or less than the macro block width. Therefore, there is a problem that even if a buffer block is additionally arranged around a macroblock and connected to a pass-through wiring on the macroblock to reduce the wiring length, there is a limit to the length that can be shortened.

Further, in order to use the arrangement and wiring gaps in the macro block at the highest level, it is necessary to recognize an enormous amount of data such as all the arrangement and wiring information in all the used macro blocks. . Therefore, when the arrangement wiring gap in the macroblock is used as the uppermost hierarchy arrangement wiring area, there is a problem that it is difficult to cope with a large-scale circuit.

Furthermore, if the arrangement wiring density in the macroblock is high, not only is it not possible to secure an area usable for the highest hierarchy, but also if the arrangement wiring density is low, the wiring length of the wiring passing above the macroblock is reduced. There is a case where there is no optimal arrangement / wiring gap region. Therefore, there is a problem that even if the arrangement wiring gap in the macro block is used as the uppermost hierarchy arrangement wiring area, the wiring length cannot be reliably reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a hierarchical layout method for preventing rounding of wiring delay in order to solve the above problems.

[0008]

In order to achieve the above object, a hierarchical layout designing method according to the present invention is directed to a hierarchical layout designing method in a macro block, wherein the buffer for connecting the highest hierarchical wiring provided in the macro block is provided. And an uppermost layer wiring connection area, which is an area provided with the uppermost layer wiring connection buffer.

Further, in the macro block,
After arranging the buffer for connecting the highest hierarchical wiring, it is preferable to perform the arrangement and wiring in the macro block.

[0010] Further, it is preferable that after the placement and routing in the macroblock is completed, the block in the macroblock is moved and the top-level hierarchy wiring connection buffer is arbitrarily placed.

Further, before the placement and routing in the macro block, a buffer for connection of the uppermost hierarchy wiring is set in advance.
It is preferable to set in the X direction and the Y direction on the coordinate axis or any one of the directions.

After arbitrarily arranging the buffer for connecting the uppermost hierarchy wiring, the wiring in the macro block existing in the X direction and / or the Y direction is moved, and the region for the uppermost hierarchy wiring is moved. It is preferable to set it.

Further, it is preferable to use the first wiring layer in the X direction and the second wiring layer in the Y direction for the wiring in the macro block in the uppermost hierarchical wiring area.

Further, according to the hierarchical layout method of the present invention, the XY coordinates are set in the macroblock, and after the placement and routing in the macroblock is completed, the wiring connection status between the macroblocks is determined in the highest hierarchical level. A first step of judging from the wiring density and a second step of judging whether there is a wiring connected between blocks arranged in the X-direction region of the target macroblock and between external terminals among the macroblocks. A step, a third step of determining whether or not a wiring delay occurs when the wiring passes straight through the target macroblock in the X direction, and is predicted to pass in the X direction over the target macroblock. A fourth step of arbitrarily setting the number of wirings as the first wiring area for the highest hierarchy, A fifth step of determining whether there is a wiring connected between the blocks arranged in the Y direction area and between the external terminals, and a wiring delay when the wiring passes straight through the target macroblock in the Y direction. A sixth step of determining whether or not a rounding occurs, and a seventh step of arbitrarily setting the number of wirings that are predicted to pass over the target macroblock in the Y direction as a second wiring area for the highest hierarchy. An eighth step of shifting the wiring and block for the macro block overlapping the first wiring area and the second wiring area for the set top hierarchy in the vertical and horizontal directions; A ninth arrangement in which buffer blocks connectable to the above-block passing wiring are arbitrarily arranged in the first wiring area and the second wiring area for the highest hierarchy in the macro block by the number of wirings. A step, optionally placing the macroblock to the highest layer, characterized in that it comprises a tenth step of performing the layout in the highest layer.

Further, according to the hierarchical layout design method of the present invention, the XY coordinates are set in the macroblock, and the wiring connection status between the macroblocks in the uppermost hierarchy is determined from the macroblock arrangement location and the arrangement wiring density. And a second step of determining whether there is a wiring connected between blocks arranged in the X-direction area of the target macroblock and between external terminals in the macroblock. X on macroblock
A third step of determining whether or not a round-trip delay occurs when the wiring passes straight in the direction, and the number of wirings predicted to pass through the target macroblock in the X direction by the first for the highest hierarchy. Arbitrarily set as the wiring area of the macro block, and in this case, the fourth step in which the macro block wiring can be used only in the first wiring layer, and the inter-block and external terminals arranged in the Y direction area of the target macro block A fifth step of determining whether there is a wiring connected between them, and a sixth step of determining whether a rounding of a wiring delay occurs when the wiring passes straight on the target macroblock in the Y direction. And arbitrarily set the number of wirings that are predicted to pass over the target macroblock in the Y direction as the second wiring area for the highest hierarchy. Indicates a seventh step in which only the second wiring layer can be used, and a first wiring area for the highest hierarchy in the macro block, the number of buffer blocks connectable to the predicted over-block on-block wiring being arbitrarily determined by the number of wirings. Eighth step of arranging in the second wiring region, and laying out the macro block while keeping the wiring region for the highest hierarchy and the buffer block for the highest hierarchy wiring connection in the macro block. 9 and a tenth step of arranging macroblocks arbitrarily in the highest hierarchy and laying out the highest hierarchy.

In particular, the hierarchical layout method of the present invention is a means having a buffer for connecting the highest hierarchical wiring and a region for the highest hierarchical wiring in a macroblock. More specifically, the macroblock has means for preparing an area for the uppermost layer wiring in either the X direction or the Y direction or both directions, and furthermore, the uppermost layer wiring is previously stored in the macroblock. It has means for preparing a connection buffer block.

[0017]

Next, an embodiment of the present invention will be described.
This will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the hierarchical layout design method according to the present invention. In this method, in the macro block A3, a wiring area A1 for the highest hierarchy provided in the Y direction, a wiring area A2 for the highest hierarchy provided in the X direction, and a wiring A1 for the highest hierarchy are provided.
A2, and a macroblock wiring area A3 between A2 and A3.
Further, the configuration is provided with a buffer block A4 for connecting the highest hierarchy wiring arranged in a region near the intersection of the wiring region A1 for the highest hierarchy and the wiring region A2 for the highest hierarchy. In the macroblock wiring area, only the two aluminum wiring layers A7 can be used in the uppermost wiring area A2 in the X direction, and one aluminum wiring layer A7 in the uppermost wiring area A1 in the Y direction. The operation is performed with the macro block wiring being usable only in the wiring layer A6.

Next, FIG. 2 is a flowchart showing the procedure of the first embodiment of the present invention. Hereinafter, the procedure of the hierarchical layout design method of the present invention will be described in detail with reference to FIG. First, in the macro block A3,
The placement and routing is completed (step 2-1). Next, the number of top-level wirings that pass straight through the macroblock A3 and the direction of passage (wiring connection status) at the time of wiring at the highest level are determined by the arrangement position of the macroblock A3 at the highest level and the external terminal connection status. And placement density (placement wiring density)
(Step 2-2). Next, it is determined whether there is a wiring connected between the blocks arranged in the left and right regions of the target macroblock and between the external terminals (step 2-3). If there is an uppermost hierarchical wiring that passes straight in the X direction, it is determined from the shape and scale of the macroblock A3 whether or not the wiring length is long enough to cause a wiring delay (step 2-4). Here, when it is determined that the highest hierarchical wiring passing over the macroblock A3 causes a delay rounding, the highest hierarchical wiring area A in the direction in which the estimated number of wirings can be passed and the highest possible wiring is passed.
2 is set in the macro block A3 (step 2-5). After performing steps 2-3 to 2-5 for the X direction, the same is repeated for the Y direction (steps 2-6 to 2-8). That is, it is determined whether there is a wiring connected between the blocks arranged in the upper and lower regions of the target macroblock and between the external terminals (step 2-6), and Y is determined on the target macroblock A3. If there is an uppermost hierarchical wiring that passes straight in the direction, it is determined from the shape and scale of the macroblock A3 whether or not the wiring length is long enough to cause a delay in wiring delay (step 2-7). If it is determined that the highest-level wiring that passes over the macroblock A3 causes a delay rounding, the highest-level wiring area A1 is set as the highest-level wiring area A1 in the direction in which the width that can be passed by the predicted number of wirings is predicted. It is set in block A3 (step 2-8). Next, the set wiring area A for the highest hierarchy
The wirings and blocks in the macro block A3 that overlap the lines 1 and A2 are shifted to the nearest upper, lower, left and right regions (step 2-9). At this time, the wiring A6 in the macroblock passing through the wiring area A1 for the highest hierarchy in the Y direction in the macroblock A3 is only one aluminum wiring layer, and the wiring A6 in the macroblock passing the wiring area A2 for the highest hierarchy in the X direction. Wiring A
7 has only two aluminum wiring layers. Subsequently, the buffer layer A4 for the number of wirings for the highest hierarchy predicted to pass over the macroblock A3 is used for the connection of the highest hierarchy wiring in the predicted direction and the wiring region A1 or A for the highest hierarchy.
2 (Step 2-10). that time,
The buffer layer A4 is connected to the highest hierarchical wiring passing over the macroblock A3, so that the wiring length is set so that the wiring delay does not occur. In this way, the layout at the highest level is performed (step 2).
-11). Macro block A3 in the highest hierarchy
The internal layout wiring information is only wiring information and additional buffer block information existing in the wiring areas A1 and A2 for the highest hierarchy. That is, only the number and coordinates of the buffer blocks and the terminal information and shape of the macro block are provided.

Next, FIG. 3 is a schematic diagram showing a change in state according to the procedure of FIG. First, B1 is a diagram in which the placement and routing in the macroblock is completed,
The state after the end of -1 is shown. Next, B2 is a diagram in which the highest hierarchical wiring area is set in the macroblock, and shows a state after the above-described steps 2-5 and 2-8. B3 is a diagram in which wiring and blocks overlapping the wiring area for the highest hierarchy are shifted up, down, left, and right, and show a state after the above-described step 2-9. Further, B4 is located in the top-level wiring area.
FIG. 13 is a diagram in which a buffer block for connecting the highest hierarchical wiring is arbitrarily arranged, and shows a state after step 2-11 described above.

Next, the effect of the first embodiment of the present invention will be described. In the first embodiment of the present invention, the processing is performed on the macro block A3 which has been arranged and routed in advance. In addition, since the shift width of the arrangement and wiring result in the macro block A3 is expected to be about several to several tens of wiring grids, the timing characteristics in the macro block A3 are not changed as much as the hierarchical layout macro block without greatly deteriorating. Can be diverted. In addition, since this embodiment is performed on a macro block for which arrangement and wiring have been completed in advance, an area for the highest hierarchy can be set according to various wiring connection states of the highest hierarchy. Further, since only one aluminum wiring layer exists in the wiring area A1 for the uppermost hierarchy in the Y direction in advance, the wiring for the uppermost hierarchy in the Y direction can freely use the two aluminum wiring layers, and the wiring can be performed without any trouble. Becomes possible. Similarly, since only the two aluminum wiring layers exist in the uppermost hierarchical wiring area A2 in the X direction, the uppermost hierarchical wiring in the X direction can use one aluminum wiring layer freely, and the wiring can be performed without any trouble. It becomes possible. In the wiring layers A1 and A2 for the highest hierarchy in the macro block A3,
One aluminum layer in the X direction and two aluminum layers in the Y direction can be used freely, and the wiring length of the wiring passing over the macro block A3 can be reduced without difficulty even in a hierarchical layout design with low-layer wiring.

FIG. 4 is a flowchart showing a second embodiment of the present invention. In this embodiment, first, the position of each macro block to be arranged in the highest hierarchy is determined. Next, at the time of wiring in the highest hierarchy, the number and passing direction of the highest hierarchy wiring that passes straight on the macroblock A3 are predicted from the arrangement position, the arrangement density, and the external terminal connection status of the macroblock A3 in the highest hierarchy. (Step 4-1). next,
It is determined whether there is a wiring to be connected between the blocks arranged in the left and right regions of the target macroblock and between the external terminals (step 4-2).
If it is predicted that there is a top-level wiring that passes straight through on the line 3, it is determined from the shape and scale of the macroblock A3 whether or not the wiring length will be long enough to cause a rounding of wiring delay (step 4-3). . Macro block A3
When it is determined that the uppermost hierarchical wiring passing therethrough causes a delay rounding, the uppermost hierarchical wiring area A2 is formed in the direction in which the width that can be passed by the predicted number of wirings is predicted to pass.
Set in macro block A3. At this time, only two aluminum wirings are allowed in the macro block (step 4).
-4). Next, similarly in the Y direction, first, it is determined whether there is a wiring to be connected between the blocks arranged in the upper and lower regions in the target macroblock and between the external terminals (step 4-5). ), If the wiring passes straight through the target macroblock in the Y direction, it is determined whether or not a wiring delay is caused (step 4-6). If it is determined that a wiring delay is caused, the predicted number of wirings is passed. The highest level wiring area A1 is set in the macroblock in the direction in which the possible wave b is predicted to pass. that time,
Only one aluminum wiring is allowed in the macro block (step 4-7). Next, buffer blocks that can be connected to the predicted macroblock pass-through wiring are arbitrarily set to the number of wiring lines, the highest hierarchy wiring area A1 in the macroblock.
It is arranged in A2 (step 4-8). Next, a layout in the macro block is performed with the wiring area for the highest hierarchy and the buffer block for the highest hierarchy connected in the macro block (step 4-9). Finally, a macro block is arbitrarily arranged in the highest hierarchical level, and layout is performed in the highest hierarchical level (step 4-10). In step 4-4 and step 4-7, the wiring A6 in the macroblock passing through the wiring area A1 for the highest hierarchy in the Y direction in the macroblock A3 has only one aluminum wiring layer and the wiring for the highest hierarchy in the X direction. The intra-macro-block wiring A7 passing through the region A2 has only two aluminum wiring layers. Subsequently, as many buffer blocks A4 as the number of wirings for the highest hierarchy predicted to pass over the macroblock A3 are arbitrarily arranged in the wiring direction A1 or A2 for the highest hierarchy as tangents to the highest hierarchy wiring in the predicted direction. I do. that time,
The buffer layer A4 is connected to the highest hierarchical wiring passing over the macroblock A3, so that the wiring length is set so that the wiring delay does not occur. continue,
The layout in the macro block is performed in a state in which the wiring area for the highest hierarchy and the buffer block for the highest hierarchy connection are arranged in the macro block. The arrangement wiring information in the macro block A3 in the highest hierarchy is only wiring information and additional buffer block information existing in the wiring layers A1 and A2 for the highest hierarchy.

FIG. 5 is a diagram showing a state following the procedure of FIG. First, C1 is a diagram in which only the shape in the macroblock is determined, C2 is a diagram in which the highest hierarchical wiring region is set in the macroblock, and C3 is a diagram in which the highest hierarchical wiring region is set in the highest hierarchical wiring region. FIG. 4 is a diagram in which a hierarchical wiring connection buffer block is arbitrarily arranged, and C4 is a diagram in which arrangement and wiring within a macro block is completed.

Next, the effect of the second embodiment of the present invention will be described. In the second embodiment of the present invention, the wiring in the macro block A3 is performed in a state where the wiring layers A1 and A2 for the uppermost hierarchy and the buffer block A4 for connecting the uppermost hierarchy are arranged in advance. Therefore, since the timing verification in the macro block A3 including the wiring layers A1 and A2 for the uppermost hierarchical wiring and the buffer block for the uppermost hierarchical wiring connection can be performed, once the macro block is created, the timing verification is never performed again. There is no need to confirm.

Next, a third embodiment of the present invention will be described in detail. Although the first and second embodiments and the flow are completely the same, the only difference is that the buffer block for the highest hierarchical wiring connection is not pre-arranged in the highest hierarchical wiring areas A1 and A2 in the macroblock A3. It is.

Next, the effect of the third embodiment of the present invention will be described. In the second embodiment of the present invention, since only the uppermost-level wiring areas A1 and A2 are prepared in advance, the uppermost-level wiring can move between macroblocks, and the uppermost-level wiring area In this case, the block for the highest hierarchy can be arbitrarily arranged. In other words, even in various wiring connection situations, a buffer block to be connected to the macroblock passing wiring can be prepared simply by arbitrarily adding a buffer block to the circuit connection information of the highest hierarchy, and the macroblock passing wiring can be shortened. It becomes possible.

[0027]

As described above, in the hierarchical layout design method of the present invention, even when a plurality of macroblocks exist, the uppermost hierarchy is not used, and the uppermost hierarchy prepared in advance in the macroblock is not used. A wiring area and a buffer block for connecting the highest hierarchical wiring are used. Therefore,
Even when a plurality of macroblocks exist on the uppermost layer and the arrangement density on the uppermost layer is high, it is possible to reduce the length of wiring passing through the macroblocks, and it is possible to reliably prevent a delay in wiring delay.

In addition, since the buffer block for the highest hierarchy is additionally arranged in the macro block in advance regardless of the shape and the scale of the macro block, the highest hierarchy wiring to pass over the macro block is And the length of the wiring passing over the macro block can be reduced. Therefore, regardless of the size and shape of the macro block, it is possible to reduce the length of the wiring passing over the macro block, and it is possible to reliably prevent the wiring delay from being rounded.

Further, all the arrangement and wiring information in the macro block is not stored in the uppermost hierarchy, and only a small amount of data such as information on the wiring region for the uppermost hierarchy and information on the additionally arranged buffer block in the macro block is used. it can. Therefore, even a large-scale circuit can be handled.

Still further, in the macro block,
Since the wiring region for the highest hierarchy in the X direction uses only two aluminum wiring layers and the wiring region for the highest hierarchy in the Y direction uses only one aluminum wiring layer, the X direction in the highest hierarchy is
One aluminum wiring layer can be used freely, and in the Y direction, two aluminum wiring layers can be used freely. Therefore,
This means that a hierarchical layout can be easily realized even when the wiring layer of the highest hierarchical level is three levels.

According to the hierarchical layout method of the present invention, the uppermost hierarchical wiring can be traversed, and the uppermost hierarchical wiring is connected to the uppermost wiring connecting buffer block previously arranged in the macro block. In addition, wiring delay does not occur.

Therefore, the highest-level wiring can be efficiently traversed in the macroblock, and the highest-level wiring is connected to the highest-level wiring connection buffer block previously arranged in the macroblock. This is because wiring delay does not occur.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a macroblock according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a first embodiment of the present invention.

FIG. 3 is a schematic diagram showing a state according to the procedure of the first embodiment shown in FIG. 2;

FIG. 4 is a flowchart showing a second embodiment of the present invention.

FIG. 5 is a schematic view showing a state according to the procedure of the second embodiment shown in FIG. 4;

FIG. 6 is a schematic diagram of a conventional macroblock.

[Explanation of symbols]

A1 Wiring area for the highest hierarchy in the Y direction (2 aluminum wiring layers can be used freely) A2 Wiring area for the highest hierarchy in the X direction (1 aluminum wiring layer can be used freely) A3 Macroblock A4 Buffer block A5 arbitrarily arranged for connection to the uppermost hierarchy wiring A5 Block already arranged in macroblock A6 Wiring in macroblock already wired (1 in X direction) A7 Defined in the macroblock wiring already routed in the uppermost layer wiringable area in the X direction (only aluminum wiring layer in the Y direction is allowed) A8 Macroblock arrangement wiring area B1 Diagram of completion of placement and routing in macro block B2 Diagram of top-level wiring area set in macro block B3 Top-level wiring area B4 A diagram in which the wiring and blocks are shifted up, down, left and right. B4 A diagram in which the buffer block for the top layer wiring connection is arbitrarily arranged in the top layer wiring region. Figure C3 in which a top-level wiring connection buffer block is arbitrarily placed in the top-level wiring area C4 Figure in which placement and routing within a macro block is completed D1 Macro block D2 D3 Additional buffer block D4 Block already placed in macro block D5 Wiring already wired in macro block

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21 / 82,27 / 118

Claims (2)

(57) [Claims] An XY coordinate is set in a macro block, and after the placement and routing in the macro block is completed, a wiring connection state between the macro blocks is determined from a macro block arrangement location and the wiring density in the highest hierarchy. A first step, and a second step of determining whether there is a wiring connected between blocks arranged in the X-direction region of the target macroblock and between external terminals among the macroblocks, A third step of judging whether or not a wiring delay is rounded when the wiring passes straight on the target macroblock in the X direction; and the number of wirings predicted to pass in the X direction on the target macroblock. A fourth step of arbitrarily setting a minute as a first wiring area for the highest hierarchy; A fifth step of determining whether there is a wiring connected between the blocks arranged in the direction region and between the external terminals, and a wiring delay rounding when the wiring passes straight through the target macroblock in the Y direction. Sixth to determine if
And a seventh step of arbitrarily setting the number of wirings that are predicted to pass on the target macroblock in the Y direction as the second wiring area for the highest hierarchy. Eighth step of shifting the macroblock wiring and the block overlapping the first wiring area and the second wiring area for the upper layer in the vertical and horizontal directions, and connecting to the predicted passing wiring on the macroblock. A ninth step of arranging possible buffer blocks in the first wiring area and the second wiring area for the highest hierarchy in the macroblock arbitrarily by the number of wirings; A tenth step of arbitrarily arranging and laying out at the highest hierarchical level. 2. A first step of setting XY coordinates in a macroblock, and judging the wiring connection status between the macroblocks in the highest hierarchy from the macroblock arrangement location and the arrangement wiring density. A second step of determining whether there is a wiring connected between the blocks arranged in the X-direction region of the target macroblock and between the external terminals, and in the X direction on the target macroblock. A third step of judging whether or not a rounding delay occurs when the wiring passes straight ahead; and a first wiring for the top hierarchy for the number of wirings predicted to pass in the X direction on the target macroblock. A fourth step of arbitrarily setting the wiring area as the wiring area, in which the macroblock wiring can be used only in the first wiring layer; A fifth step of determining whether there is a wiring connected between the blocks arranged in the Y-direction region of the block and between the external terminals, and a case where the wiring goes straight through the target macroblock in the Y-direction. A sixth step of determining whether or not a rounding of a wiring delay occurs; and arbitrarily setting a number of wirings predicted to pass through the target macroblock in the Y direction as a second wiring area for the highest hierarchy. At this time, a seventh step in which only the second wiring layer can be used for the macroblock wiring, and arbitrarily setting the number of buffer blocks connectable to the predicted macroblock passing-through wiring by the number of wirings in the macroblock. An eighth step of arranging in the first wiring region and the second wiring region for the upper hierarchy, a wiring region for the highest hierarchy and a top in the macro block. A ninth step of laying out the macroblocks with the hierarchical wiring connection buffer block still being arranged, and a tenth step of arbitrarily arranging the macroblocks in the highest hierarchy and laying out the top hierarchy. A hierarchical layout design method, comprising: