JP5035003B2 - Wiring layout apparatus, wiring layout method, and wiring layout program - Google Patents

Description

  The present invention relates to a wiring layout device, a wiring layout method, and a wiring layout program, which relate to a wiring layout device, a wiring layout method, and a wiring layout program for laying out a wiring having an adjacent prohibited wiring area only on one side (for example, one side adjacent prohibited wiring). .

  In recent years, wiring of a semiconductor device (hereinafter referred to as an LSI) or an electronic circuit board (hereinafter referred to as a PCB (Printed Wiring Board)) is performed by automatic placement and routing using an arithmetic device. In addition, the wiring density of LSIs and PWBs is increasing with the improvement of processing accuracy. When wiring is performed at a high density, the clock signal may receive interference noise from adjacent wiring, resulting in a circuit failure such as signal delay. This interference noise is generated due to the parasitic capacitance formed between the wirings. Therefore, in order to reduce the interference noise, it is necessary to increase the distance between the wiring that becomes a noise source such as the clock wiring and the other wiring.

In view of this, Patent Documents 1 and 2 disclose a method of performing automatic placement and routing while securing a distance between a wiring that becomes a noise source and another wiring. In Patent Document 1, by using a wiring map that stores the state of wiring type wiring adjacent prohibition and wiring type via adjacent prohibition for each lattice point, the mounting density is reduced in LSI wiring design when there are a plurality of line types. A wiring design method that prohibits adjoining is not proposed. Further, in Patent Document 2, when determining the wiring pattern of the gate array or standard cell based on the net list, the wiring interval between the clock wiring and the critical path wiring and other wirings is automatically widened. It has been proposed to reduce the delay.
JP-A-6-45442 JP-A-9-92726

  However, in the methods proposed in Patent Documents 1 and 2, there is a problem that the capacity of the wiring is lowered because other wirings are not adjacent to both sides of the wiring that becomes a noise source. FIG. 12 is a diagram for explaining this problem. In the example shown in FIG. 12, the first layer wirings 121 to 130 and the second layer wirings 131 to 140 are wired along the wiring track. A cell A having terminals 101 to 104 and a cell B having terminals 111 to 114 are arranged. Then, the terminal 102 of the cell A and the terminal 112 of the cell B are connected by the adjacent prohibition wiring (for example, clock wiring) a. In such a case, according to the methods of Patent Documents 1 and 2, an interval of one track or more is set on both sides of the adjacent prohibited wiring a. At this time, the adjacent prohibition wiring a may not necessarily be prohibited on both sides. However, in the methods of Patent Documents 1 and 2, adjacent wiring cannot be prohibited only on one side. For this reason, the methods of Patent Documents 1 and 2 have a problem in that the wiring interval is unnecessarily set, and the capacity of the wiring deteriorates.

  The present invention has been made to solve such problems, and in automatic placement and routing of LSIs and PWBs, the placement of one-sided adjacent prohibited wiring having an adjacent prohibited wiring region only on one side is enhanced while reducing noise. The purpose is to do.

  A wiring layout apparatus according to the present invention is a wiring layout apparatus that performs wiring layout of a semiconductor device or an electronic circuit board, and results in registration information of circuit elements, arrangement result information of the circuit elements, design rule information, and layout results. An information storage unit that stores wiring result information and one-side adjacent wiring prohibition designation information, an actual wiring track setting unit that sets actual wiring tracks in a layout area in which the circuit elements are arranged, and terminals of the circuit elements Arranging the circuit elements so as to be located on the actual wiring track, outputting the arrangement information, a virtual wiring track setting unit setting a virtual wiring track between the adjacent actual wiring tracks, The virtual terminal adjacent to the terminal of the circuit element to which the first wiring designated by the one-side adjacent wiring prohibition designation information is connected In accordance with the design rule information, the terminal arrangement changing unit to be moved on the line track is connected between the terminals on the actual wiring track by the second wiring along the actual wiring track, and between the terminals on the virtual wiring track. Adjacent wiring section for calculating the length of the adjacent section in which the first wiring and the second wiring are arranged adjacent to each other, and the wiring portion connecting the first wiring and the first wiring along the virtual wiring track A length calculation unit and the real wiring track adjacent to the virtual wiring track in which the first wiring is arranged, the first wiring on the real wiring track on the side where the length of the adjacent section is shortened; A wiring shape changing unit that moves the wiring and outputs the wiring result information; and a control unit that controls an operation sequence in the wiring layout apparatus.

  A wiring layout method according to the present invention is a wiring layout method for performing wiring layout of a semiconductor device or an electronic circuit board, wherein an actual wiring track is set in a grid pattern in a layout region in which circuit elements are arranged, and terminals of the circuit elements are arranged. The circuit elements are arranged so as to be positioned on the actual wiring track, a virtual wiring track is set between the adjacent actual wiring tracks, and the first wiring designated by the one-side adjacent wiring prohibition designation information is connected. The terminal of the circuit element to be moved onto the adjacent virtual wiring track, the terminals on the actual wiring track are connected by the second wiring along the actual wiring track, and the terminals on the virtual wiring track Between adjacent sections where the first wiring and the second wiring are arranged adjacent to each other by connecting the first wiring along the virtual wiring track. The actual wiring track adjacent to the virtual wiring track on which the first wiring is arranged, and the first wiring is placed on the real wiring track on the side where the length of the adjacent section is shortened. Move the wiring.

  A wiring layout program according to the present invention is a wiring layout program for causing a computer to execute a wiring layout of a semiconductor device or an electronic circuit board based on information of a circuit element read from an information storage unit, and a layout area in which the circuit element is arranged Set a real wiring track in a grid pattern, arrange the circuit element so that the terminal of the circuit element is located on the real wiring track, set a virtual wiring track between the adjacent real wiring tracks, The terminal of the circuit element to which the one side adjacent prohibition wiring designated by the one side adjacent wiring prohibition designation information is connected is moved onto the adjacent virtual wiring track, and between the terminals on the actual wiring track along the actual wiring track. Are connected by normal wiring arranged between the terminals on the virtual wiring track. Connected by the one-sided adjacent forbidden wiring arranged along the line, calculating the distance between adjacent sections where the normal wiring and the one-sided adjacent prohibited wiring are arranged adjacently, and the one-sided adjacent prohibited wiring is arranged The real wiring track adjacent to the virtual wiring track, the one-side adjacent prohibited wiring is moved onto the real wiring track on the side where the length of the adjacent section is shortened, and wiring result information when wiring is completed is the information A wiring layout program to be output to the storage unit.

  The wiring layout apparatus, the wiring layout method, and the wiring layout program according to the present invention can increase the capacity of wiring by performing wiring using one-side adjacent prohibited wiring while enhancing the noise reduction effect.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a wiring layout device 1 according to the first exemplary embodiment of the present invention. As shown in FIG. 1, the wiring layout apparatus 1 includes a control unit 10, an actual wiring track setting unit 11, an element placement unit 12, a virtual wiring track setting unit 13, a terminal placement change unit 14, a wiring unit 16, and an adjacent wiring section length calculation. Section 18, wiring shape changing section 19, and information storage section 20.

  The control unit 10 operates the real wiring track setting unit 11, the element arranging unit 12, the virtual wiring track setting unit 13, the terminal arrangement changing unit 14, the wiring unit 16, the adjacent wiring section length calculating unit 18, and the wiring shape changing unit 19. Control the order.

  The actual wiring track setting unit 11 sets actual wiring tracks in a grid pattern in a layout area in which circuit elements are arranged. Here, the actual wiring track is arranged in a grid pattern at a predetermined interval and serves as a reference for the position where the circuit element and the wiring are arranged. In the following description, it is assumed that wiring is performed across a plurality of layers. In addition, the first layer wiring is a main direction extending from a track extending in a first direction (for example, the X direction) among the actual wiring tracks arranged in a grid, and the second direction (for example, the Y direction). The track extending in the direction of the secondary axis is taken as the secondary axis direction. Further, the second layer wiring, which is the upper wiring layer of the first layer, is a track extending in the X direction, with the track extending in the Y direction as a main axis direction among the actual wiring tracks arranged in a grid pattern. Is the minor axis direction. In addition, it is assumed that main wiring is provided along the main axis direction in both the first layer and the second layer. Further, vias or circuit element terminals connecting the wiring layers are also arranged on the actual wiring track.

  The element placement unit 12 reads the layout physical library information 21 stored in the information storage unit 20 and extracts information on circuit elements (hereinafter referred to as cells) from the layout physical library information. Then, the cells are arranged so that the extracted cell terminals are positioned on the actual wiring track. When the cell arrangement is completed, the element arrangement unit 12 outputs arrangement result information 22 to the information storage unit 20.

  The virtual wiring track setting unit 13 sets a virtual wiring track between adjacent real wiring tracks. In the present embodiment, the virtual wiring track is set along a position that equally divides the distance between adjacent real wiring tracks. The virtual wiring track is a wiring track that temporarily arranges a first wiring to be described later, and the terminals and wirings of the circuit elements are not arranged on the virtual wiring track after the wiring layout is completed.

  The terminal arrangement changing unit 14 is connected to the first wiring (the wiring that becomes the one-side adjacent prohibited wiring after the wiring layout is completed) that connects the net specified by the one-side adjacent wiring prohibited specification information 25 stored in the information storage unit 20. Move the cell terminal position on the virtual wiring track. Further, the terminal arrangement changing unit 14 includes a wiring rule changing unit 15. The wiring rule changing unit 15 changes the wiring rule for the first wiring in the design rule information 23 stored in the information storage unit 20. Details of the wiring rule changing method will be described later.

  In accordance with the design rule information 23 stored in the information storage unit 20, the wiring unit 16 connects the terminals on the actual wiring track with the second wiring arranged along the actual wiring track, and the terminals on the virtual wiring track. The first wiring one-side adjacent prohibition wirings are connected between the two along the virtual wiring track. The wiring unit 16 includes a wiring track switching unit 17. The wiring track switching unit 17 switches a track to be wired between an actual wiring track and a virtual wiring track. That is, when the wiring track switching unit 17 sets the wiring target track as an actual wiring track, the wiring unit 16 arranges the second wiring along the actual wiring track, and uses the wiring target track as a virtual wiring track. The wiring unit 16 arranges the second wiring along the virtual wiring track. Note that the first wiring and the second wiring are wirings having the same structure, except for the wiring attributes after the layout is completed.

  The adjacent wiring section length calculation unit 18 calculates the length of the adjacent section in which the first wiring and the second wiring are arranged adjacent to each other. The wiring shape changing unit 19 moves the first wiring onto an actual wiring track that is adjacent to the virtual wiring track on which the first wiring is arranged and has a shorter adjacent section length. . Then, the wiring shape changing unit 19 outputs the completed wiring layout to the information storage unit 20 as wiring result information 24.

  The information storage unit 20 includes a real wiring track setting unit 11, an element placement unit 12, a virtual wiring track setting unit 13, a terminal placement change unit 14, a wiring unit 16, an adjacent wiring section length calculation unit 18, and a wiring shape change by bus. The unit 19 is connected. The information storage unit 20 stores layout physical library information 21, arrangement result information 22, design rule information 23, wiring result information 24, and one-side adjacent wiring prohibition designation information 25. The layout physical library information 21, the design rule information 23, and the one-side adjacent wiring prohibition designation information 25 are information set in advance before starting the layout. On the other hand, the arrangement result information 22 is intermediate information in the layout, and the wiring result information 24 is final result information of the layout.

  Next, FIG. 2 is a flowchart showing the operation of the wiring layout apparatus 1 according to the first embodiment, and the operation of the wiring layout apparatus 1 will be described with reference to FIG. As shown in FIG. 2, in the wiring layout device 1, first, the actual wiring track setting unit 11 sets an actual wiring track in a layout area in which circuit elements are arranged (step S1). Subsequently, the element placement unit 12 reads the physical library information for layout 21 from the information storage unit 20 (step S2). The element placement unit 12 extracts cell information from the read layout physical library information 21 and performs a cell placement process (step S3). More specifically, this arrangement process is performed based on a net list indicating cell information and cell connection information. When the cell arrangement is completed, the element arrangement unit 12 outputs arrangement result information 22 indicating the cell arrangement to the information storage unit 20 as intermediate information. Thereafter, the wiring layout apparatus 1 sets a virtual wiring track by the virtual wiring track setting unit 13 (step S4). FIG. 3 shows an example of a schematic diagram of the layout after the processing up to step S4 is completed.

  In the example shown in FIG. 3, the cell A and the cell B are arranged in the layout area in which the real wiring track and the virtual wiring track are set. Cell A has terminals 31-34, and cell B has terminals 41-44. The cells A and B are arranged so that the terminals 31 to 34 and the terminals 41 to 44 are located on the actual wiring track. Note that a power supply wiring VDD and a ground wiring VSS are arranged in advance in the cells A and B.

  Subsequently, the wiring layout device 1 causes the terminal arrangement changing unit 14 to move the position of the terminal to which the first wiring designated by the one-side adjacent wiring prohibition designation information 25 is connected onto the virtual wiring track (step S5). . FIG. 4 shows a schematic diagram of the layout of FIG. 3 after the terminal position is changed. FIG. 4 shows an example in which it is designated by the one-side adjacent wiring prohibition designation information 25 that the first wiring is connected to the terminal 32 and the terminal 42. In FIG. 4, the terminal 32a and the terminal 42a are shown as the terminals to which the terminal 32 and the terminal 42 are moved. Note that the terminal arrangement changing unit 14 leaves the terminals 32 and 42 before the movement even after setting the terminals 32a and 42a after the movement.

  Next, the terminal arrangement changing unit 14 reads the design rule information 23 by using the wiring rule changing unit 15 and changes the wiring rule included in the design rule information 23 (step S6). Here, FIG. 5 shows an example of the wiring rule before the change, and FIG. 6 shows the wiring rule after the change. An example of changing the wiring rule will be described with reference to FIGS. The wiring rule shown in FIG. 5 shows a wiring rule applied to the second wiring (normal wiring in the drawing). In the wiring rule before the change, W1 is set as the minimum line width of the wiring, and the minimum distance between the wirings is set as W2. The minimum line width W1 and the minimum distance W2 are applied to the first wiring. On the other hand, the changed wiring rule does not change the minimum line width of the first wiring and the second wiring, but between the wirings set on both sides of the first wiring (one-side adjacent prohibited wiring in the figure). The minimum distance is set as W3. This minimum distance W3 is set larger than the minimum distance W2. For example, the minimum distance W3 is set to a distance that causes a design rule error when wiring is made to an actual wiring track adjacent to one pitch of the virtual wiring track on which the second wiring is arranged. In other words, this distance is set to a distance that can prevent the first wiring designated by the one-side adjacent wiring prohibition designation information from being placed on the adjacent virtual wiring track. If there is an adjacent wiring prohibition rule in the existing design rule information, the adjacent wiring prohibition rule can be applied as a design rule for the first wiring.

  Subsequently, the wiring layout device 1 performs a wiring process by the wiring unit 16. At this time, in this embodiment, the wiring unit 16 performs the placement process while sequentially switching the wiring target track between the real wiring track and the virtual wiring track for each wiring that the wiring track switching unit 17 performs the placement process. To do. Therefore, the wiring unit 16 determines the type of wiring to be placed next in the wiring track switching unit 17 (step S7). If it is determined in step S7 that the next wiring to be placed is the first wiring, the wiring track switching unit 17 sets the virtual wiring track as a wiring target track, and the wiring unit 16 follows the virtual wiring track. The first wiring arrangement process is performed (step S8). On the other hand, if it is determined in step S7 that the next wiring to be placed is the second wiring, the wiring track switching unit 17 sets the actual wiring track as the wiring target track, and the wiring unit 16 sets the actual wiring track. A second wiring arrangement process is performed along the line (step S9). Then, it is determined whether or not the placement processing for all the wirings has been completed after the placement processing in step S8 or step S9 is finished (step S10). If the placement process has been completed for all the wirings in step S10, the process proceeds to step S11. If there is a wiring for which the placement process has not been completed, the process returns to step S7. The wiring unit 16 sequentially repeats the processes of steps S7 to S10 for each wiring to be processed. In the wiring process in steps S8 and S9, the wiring unit 16 performs wiring while referring to the design rule information 23 changed in step S6. That is, the wiring arranged by the wiring unit 16 is arranged based on the restriction by the design rule information 23 after the change. FIG. 7 shows a schematic diagram of the layout after step S10 is completed.

  In the example shown in FIG. 7, the second wirings 50 to 60 and the first wiring C are arranged as the first layer wiring, and the second wirings 61 to 70 are arranged as the second layer wiring. The first wiring C is arranged so as to connect the terminal 32a of the cell A and the terminal 42a of the cell B. Further, the first wiring C is disposed on the virtual wiring track. The second wiring 50 is connected to the terminal 31 and further connected to the second wiring 61 in the second layer via a via (not shown). The second wiring 51 is a part of the wiring parallel to the first wiring C, and is connected to the second wiring 62 in the second layer through a via. The second wiring 52 is a wiring partially parallel to the first wiring C, and is connected to the second wirings 63 and 64 of the second layer through vias. The second wiring 63 is connected to the second wiring 53 of the first layer through a via. The second wiring 53 is connected to the terminal 33. The second wiring 54 is connected to the terminal 34 and further connected to the second wiring 65 of the second layer through a via.

  The second wiring 55 is connected to the terminal 41 and further connected to the second wiring 66 in the second layer through a via. The second wiring 56 is a part of the wiring parallel to the first wiring C, and is connected to the second wiring 67 of the second layer through a via. The second wiring 58 is a part of the wiring parallel to the first wiring C, and is connected to the second wiring 68 of the second layer through a via. The second wiring 68 is connected to the second wiring 57 in the first layer through a via. The second wiring 57 is connected to the terminal 43. The second wiring 60 is connected to the terminal 44 and is further connected to the second wiring 70 in the second layer through a via. The second wiring 59 is a wiring arranged between the second wiring 58 and the second wiring 60, and is connected to the second wiring 69 in the second layer through a via. In addition, as shown in FIG. 7, wiring is not performed to the actual terminal 32 of the cell A and the actual terminal 42 of the cell B at this time.

  Subsequently, the wiring layout device 1 calculates the length of the adjacent section in which the first wiring C and the second wiring parallel to the first wiring C are adjacent by the adjacent wiring section length calculation unit 18 (step S11). . This calculation process will be described with reference to the layout diagram of FIG. In FIG. 7, the wirings arranged above the first wiring C are the second wiring 51 and the second wiring 56. At this time, the distance between the first wiring C and the second wiring 51 is 4 tracks, and the distance between the first wiring C and the second wiring 56 is 3 tracks. Therefore, the adjacent wiring section length calculation unit 18 calculates the length of the adjacent section between the second wiring and the first wiring C arranged above the first wiring C as 7 tracks. The second wirings arranged below the first wiring C are the second wiring 52 and the second wiring 58. At this time, the distance between the first wiring C and the second wiring 52 is 3 tracks, and the distance between the first wiring C and the second wiring 58 is 5 tracks. Therefore, the adjacent wiring section length calculation unit 18 calculates the length of the adjacent section between the second wiring and the first wiring C arranged below the first wiring C as 8 tracks.

  Based on the calculation result of step S11, the wiring shape changing unit 19 changes the shape of the first wiring C (step S12). An example of the wiring shape changing process in step S12 is shown in FIG. The layout diagram shown in FIG. 8 is obtained by performing a wiring shape changing process on the layout diagram of FIG. In step S8, since the length of the upper adjacent section of the first wiring C is 7 tracks and the length of the lower adjacent section is calculated as 8 tracks, the wiring shape changing unit 19 determines that the first wiring C C is moved to an upper real wiring track having a short adjacent section length among the real wiring tracks adjacent to the virtual wiring track in which the second wiring C is arranged. In the example shown in FIG. 8, since the terminal 32 and the terminal 42 are located on the actual wiring track after movement, no further changes are made. When the wiring shape changing process is completed, the wiring shape changing unit 19 outputs the completed layout to the information storage unit 20 as the wiring result information 24. Thereby, the process of the wiring layout apparatus 1 is completed.

  From the above description, the wiring layout device 1 according to the first exemplary embodiment lays out the first wiring as a one-side adjacent prohibited wiring having an adjacent wiring prohibited region only on one side. At this time, the wiring layout device 1 calculates the length of the adjacent section between the first wiring and the second wiring adjacent to this wiring, and on the actual wiring track on the side where the length of the adjacent section becomes shorter. The first wiring is arranged. As a result, the distance between the one-side adjacent prohibited wiring and the other wiring can be minimized, and the influence of noise on the one-side adjacent prohibited wiring can be reduced. Further, by using the one-sided adjacent prohibited wiring in which the adjacent prohibited region is set only on one side, the wiring capacity can be improved.

  In the wiring layout device 1, virtual wiring tracks are set between the actual wiring tracks by the virtual wiring track setting unit 13, and the first wiring is provisionally arranged on the virtual wiring tracks. Then, the adjacent wiring section length calculation unit 18 obtains the length of the adjacent section with respect to the temporarily arranged first wiring. Thereafter, the wiring shape changing unit 19 changes the wiring shape according to the length of the adjacent section. By performing such processing in each block of the wiring layout device 1, it becomes easy to automate the recognition of the first wiring that becomes the one-side adjacent prohibited wiring and the processing related to the first wiring. In addition, with respect to the wiring rule changing unit 15 and the wiring track switching unit 17, these blocks facilitate processing automation.

Embodiment 2
The second embodiment shows another example of processing in the wiring shape changing unit 19. A layout diagram in the middle of the wiring change processing in the second embodiment is shown in FIG. 9, and a layout diagram after the wiring change processing is shown in FIG. The layout shown in FIGS. 9 and 10 is obtained by applying the wiring change process of the second embodiment to the layout of FIG.

  In the wiring shape changing process in the second embodiment, first, the section (the section adjacent to the second wiring 58) having the maximum five tracks among the lengths of the adjacent sections calculated in step S11 in FIG. The first wiring C (in FIG. 9, the first wiring arranged on the actual wiring track) in the empty area (the area facing the second wiring 58 and having no wiring adjacent to the first wiring C). The wiring shape of the wiring C) is changed (see FIG. 9). Specifically, the wiring change process is performed by replacing the segment that is the target of the wiring change process with the actual wiring track on the second wiring 56 side having a short adjacent section. At this time, the first wiring C in the portion where the tracks have been replaced and the first wiring C in the portion where the tracks have not yet been replaced become discontinuous. Connect with secondary axis wiring.

  Subsequently, the calculation processing of the adjacent section in step S11 is performed again for the first wiring C on which the track is not replaced in the stage of FIG. Then, the wiring shape changing process is performed for the first wiring C having the maximum length of the adjacent section in the calculation process. In the stage of FIG. 9, in the segment where the track is not replaced, the first wiring C sandwiched between the second wiring 51 and the second wiring 52 is the target of the calculation process in step S11. The calculated length of the adjacent section is a section (the section adjacent to the second wiring 51) having the maximum four tracks and the subsequent empty area (the area facing the second wiring 51, The wiring shape is changed for the first wiring C (the first wiring C arranged on the actual wiring track on the second wiring 52 side in FIG. 10) in the first wiring C (the area without the wiring adjacent to the first wiring C). (See FIG. 10). Specifically, the wiring change process is performed by replacing the segment that is the target of the wiring change process with an actual wiring track on the second wiring 52 side having a short adjacent section. At this time, the terminal 32 and the first wiring C are not connected, but the unconnected portion is connected by wiring in the sub-axis direction. Note that the wirings can be replaced in an order different from the above description.

  That is, in the second embodiment, the first wiring C that is the one-side adjacent prohibition wiring is arranged so as to be located on a different actual wiring track for each adjacent section. As a result, the first wiring C in FIG. 10 has a bent shape. In the second embodiment, the wiring shape changing process in step S12 is performed on the segment having the maximum length of the adjacent section calculated in the adjacent section calculation process in step S11. These processes are repeated every time the process for one segment is completed. That is, by repeatedly performing the processing of step S11 and step S12 described above in order from the segment having the longer adjacent section, the wiring shape is preferentially changed for the segment having the longer adjacent section. Accordingly, the segment having a short adjacent section is processed first, and the wiring shape changing process of the segment having a long adjacent section is prevented from being hindered by the short segment of the adjacent section.

  In this way, by changing the actual wiring track in which the first wiring C is arranged for each section, the length of the adjacent section between the first wiring C that becomes the one-side adjacent prohibited wiring and the other wiring is made shorter. Can do. Thereby, the effect of reducing the influence of noise on the one-side adjacent prohibited wiring C can be further enhanced.

Embodiment 3
The third embodiment shows another example of processing in the wiring shape changing unit 19. FIG. 11 shows a layout diagram after performing the wiring change process in the third embodiment. In the layout shown in FIG. 11, the global power supply wiring GVDD is arranged above the first wiring C. The global power supply wiring GVDD is connected to the power supply wiring VDD of the cell A and the cell B through the second wiring 71 and vias 72a to 72f of the second layer. Further, the global power supply wiring GVDD is disposed adjacent to the first wiring C. The wiring change process of the second embodiment is applied to the layout of FIG.

  In the wiring shape changing process according to the third embodiment, when the first wiring C is adjacent to the low-impedance wiring having no potential change like the power wiring, the first wiring C is powered regardless of the length of the adjacent section. Place on the actual wiring track on the wiring side. Since the low impedance wiring does not become a noise generation source, even if the first wiring C disposed as a one-side adjacent prohibition wiring is disposed adjacent to the low impedance wiring, the first wiring is not easily affected by noise.

  Therefore, when the low impedance wiring is adjacent to the first wiring C, the noise reduction effect and the wiring capacity can be achieved by arranging the first wiring C so as to be adjacent to the low impedance wiring regardless of the length of the adjacent section. The effect which improves can be acquired.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, although the wiring layout apparatus for realizing the wiring layout method has been described in the above embodiment, each operation in the wiring layout apparatus can be performed by a computer such as a general-purpose computer by a program. It is also possible to designate a wiring that does not want to be affected by noise as the one-side adjacent prohibition wiring.

1 is a block diagram of a wiring layout device according to a first exemplary embodiment; 3 is a flowchart showing an operation of the wiring layout apparatus according to the first exemplary embodiment; 3 is an example of a layout generated in the wiring layout device according to the first exemplary embodiment; It is a figure which shows the example of the wiring rule before the change concerning Embodiment 1. FIG. It is a figure which shows the example of the wiring rule after the change concerning Embodiment 1. FIG. 3 is an example of a layout generated in the wiring layout device according to the first exemplary embodiment; 3 is an example of a layout generated in the wiring layout device according to the first exemplary embodiment; 3 is an example of a layout generated in the wiring layout device according to the first exemplary embodiment; 12 is an example of a layout in the middle of a wiring change process according to the second embodiment; 10 is an example of a layout after completion of the wiring change process according to the second embodiment. 13 is an example of a layout generated in the wiring layout apparatus according to the third embodiment. It is an example of the layout produced | generated by the conventional layout method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring layout apparatus 10 Control part 11 Real wiring track setting part 12 Element arrangement part 13 Virtual wiring track setting part 14 Terminal arrangement change part 15 Wiring rule change part 16 Wiring part 17 Wiring track switching part 18 Adjacent wiring section length calculation part 19 Wiring Shape changing unit 20 Information storage unit 21 Physical library information for layout 22 Placement result information 23 Design rule information 24 Wiring result information 25 One-side adjacent wiring prohibition designation information 31 to 34, 32a, 41 to 44, 42a Terminals 50 to 71 Wiring 72a-72f Via A, B Cell C 1st wiring GVDD Global power supply wiring VDD Power supply wiring VSS Grounding wiring W1 Minimum line width W2, W2 Minimum distance

Claims (16)

A wiring layout device for performing wiring layout of a semiconductor device or an electronic circuit board,
An information storage unit that stores circuit element registration information, circuit element placement result information, design rule information, wiring result information resulting in a layout, and one-side adjacent wiring prohibition designation information;
An actual wiring track setting unit for setting actual wiring tracks in a grid pattern in a layout region in which the circuit elements are arranged;
Placing the circuit element such that the terminal of the circuit element is located on the actual wiring track, and outputting the placement result information;
A virtual wiring track setting unit that sets a virtual wiring track between the adjacent real wiring tracks;
A terminal arrangement changing unit that moves the terminal of the circuit element to which the first wiring designated by the one-side adjacent wiring prohibition designation information is connected onto the adjacent virtual wiring track;
According to the design rule information, the terminals on the actual wiring track are wired by the second wiring along the actual wiring track, and the terminals on the virtual wiring track are routed along the virtual wiring track by the first wiring. A wiring section for wiring, and
An adjacent wiring section length calculation unit for calculating a length of an adjacent section in which the first wiring and the second wiring are arranged adjacent to each other;
Moving the first wiring onto the actual wiring track adjacent to the virtual wiring track on which the first wiring is disposed, on the side where the length of the adjacent section is shortened; A wiring shape changing unit for outputting the wiring result information;
A control unit for controlling the operation sequence in the wiring layout device;
Wiring layout apparatus having   The wiring layout apparatus according to claim 1, wherein the wiring shape changing unit arranges the first wiring along the actual wiring track that is different for each section.   When the first wiring and the low-impedance wiring are adjacent to each other, the wiring shape changing unit includes the first wiring along the actual wiring track adjacent to the low-impedance wiring regardless of the length of the adjacent section. The wiring layout device according to claim 1, wherein: The adjacent wiring section length calculation unit calculates the length of the adjacent section for a wiring having an inter-wiring distance of 2 tracks or less among the first wiring and the second wiring running in parallel. The wiring layout apparatus according to 1.   The terminal arrangement changing unit is configured such that a distance that causes a design rule error when wiring is performed on the real wiring track adjacent to one pitch adjacent to the virtual wiring track on which the first wiring is disposed is a wiring prohibited area. The wiring layout apparatus according to claim 1, further comprising a wiring rule changing unit that sets the wiring rule to be   The wiring layout apparatus according to claim 1, wherein the wiring unit includes a wiring track switching unit that switches a track to be wired between the real wiring track and the virtual wiring track. A wiring layout method for performing wiring layout of a semiconductor device or an electronic circuit board by a computer using information on circuit elements read from an information storage unit ,
By the processing of the computer,
Set the actual wiring tracks in a grid pattern in the layout area where circuit elements are placed,
Arranging the circuit elements so that the terminals of the circuit elements are located on the actual wiring track,
A virtual wiring track is set between the adjacent actual wiring tracks,
Moving the terminal of the circuit element to which the first wiring specified by the one-side adjacent wiring prohibition designation information stored in the information storage unit is connected to the adjacent virtual wiring track;
The terminals on the actual wiring track are connected by a second wiring arranged along the actual wiring track,
The terminals on the virtual wiring track are connected by the first wiring along the virtual wiring track,
Calculating a length of an adjacent section in which the first wiring and the second wiring are arranged adjacent to each other;
Wherein a real wiring tracks adjacent to the virtual line tracks the first wiring are arranged to move the first wire to the length of the adjacent sections is shorter sides of the actual wiring on the track ,
A wiring layout method for outputting wiring result information for which wiring has been completed to the information storage unit .   The wiring layout method according to claim 7, wherein the first wiring is arranged along the actual wiring track that is different for each section.   The wiring layout method according to claim 7, wherein when the low-impedance wiring is adjacent, the first wiring is arranged along the actual wiring track adjacent to the low-impedance wiring regardless of the length of the adjacent section. . The wiring layout method according to claim 7, wherein the length of the adjacent section is calculated for a wiring having a distance between wirings of 2 tracks or less among the first wiring and the second wiring that run in parallel .   8. The wiring layout method according to claim 7, wherein the wiring layout method sets a wiring rule with a region including the real wiring track adjacent to one pitch next to the virtual wiring track as a wiring prohibited region. A wiring layout program for causing a computer to execute a wiring layout of a semiconductor device or an electronic circuit board based on information on circuit elements read from an information storage unit,
An actual wiring track is set in a grid pattern in the layout area where the circuit elements are arranged,
Arranging the circuit elements so that the terminals of the circuit elements are located on the actual wiring track,
A virtual wiring track is set between the adjacent actual wiring tracks,
Moving the terminal of the circuit element to which the first wiring specified by the one-side adjacent wiring prohibition designation information stored in the information storage unit is connected to the adjacent virtual wiring track;
Connecting the terminals on the actual wiring track with the second wiring along the actual wiring track;
Wherein along the terminals on the virtual wiring tracks to the virtual wiring tracks are connected by the first wiring,
Calculating a length of an adjacent section in which the first wiring and the second wiring are arranged adjacent to each other;
Moving the first wiring onto the actual wiring track adjacent to the virtual wiring track on which the first wiring is disposed, on the side where the length of the adjacent section is shortened;
A wiring layout program for outputting wiring result information on completion of wiring to the information storage unit.   13. The wiring layout program according to claim 12, wherein the first wiring is arranged along the actual wiring track that is different for each section.   13. The wiring layout program according to claim 12, wherein when the low impedance wiring is adjacent, the first wiring is arranged along the actual wiring track adjacent to the low impedance wiring regardless of the length of the adjacent section. . The wiring layout program according to claim 12, wherein the length of the adjacent section is calculated for a wiring having a distance between wirings of two tracks or less among the first wiring and the second wiring that run in parallel .   13. The wiring layout program according to claim 12, wherein the wiring layout method sets a wiring rule with a region including the actual wiring track adjacent to the virtual wiring track as a wiring prohibited region.

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