JP2007066974A - Semiconductor integrated circuit and method of laying out the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To arrange interconnections easily, even when the priority wiring direction of an interconnection layer wherein an in-cell power supply trunk line is to be formed is set different from the direction of the cell row. <P>SOLUTION: After logic cells whose in-cell power supply trunk line is arranged in a first interconnection layer are arranged (S102), interstitial cells whose in-cell power supply line is arranged in a second interconnection layer are arranged (S103) at a position where the logic cells are not arranged. Thus, in a subsequent inter-cell signal interconnection processings (S104), signal interconnections oriented in the direction of intersecting the in-cell power supply trunk lines can be arranged in the first interconnection layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a layout method using a layout apparatus that determines the arrangement of cells and wirings.

  In the semiconductor integrated circuit, a wiring for connecting each element is formed so as to pass through one or a plurality of wiring layers. In layout design, the wiring of each wiring layer is generally formed in a direction along a preferential wiring direction (such as a horizontal direction or a vertical direction) preset for each wiring layer. By setting such a priority wiring direction, it is possible to easily reduce wiring congestion and increase design efficiency. The priority wiring direction is often set to a different direction in each wiring layer adjacent to the direction perpendicular to the substrate (see, for example, Patent Document 1).

  Here, if each wiring layer is called the first wiring layer, the second wiring layer, etc. in order from the side closest to the substrate, the priority wiring direction of the first wiring layer is generally set to the same direction as the cell row. Often. This is due to the following reason. That is, in general, the in-cell power supply main line that becomes the main line of the power supply wiring in the cell is advantageously formed mainly by using the first wiring layer because it is necessary to supply a potential to the diffusion region of the cell. The in-cell power supply trunk line is provided along two opposing sides of the cell. When a cell row is formed, each cell is arranged so that the in-cell power supply trunk line is continuous. Therefore, since many wirings in the same direction as the cell row are formed in the first wiring layer, setting the direction as the priority wiring direction reduces the crossing of the wirings, and makes efficient wiring. It often becomes easier.

  However, with the diversification of semiconductor integrated circuits and the like, it is a fact that the priority wiring direction of the first wiring layer may need to be set to a direction different from the cell row depending on various conditions. In this case, the wiring that intersects the in-cell power supply trunk line formed of the first wiring layer cannot be formed in the same first wiring layer, so that the difficulty of wiring increases. Specific examples will be described below.

  FIG. 43 is formed so that the cell rows are arranged in the horizontal direction of the figure, and the priority wiring directions of the first wiring layer and the third wiring layer are set to the vertical direction, and the priority wiring of the second wiring layer is set. It is a top view which shows the example of a layout when a direction is set to a horizontal direction. In the example of the figure, inter-cell wirings 2001 to 2003, cells 2004 and 2005, and in-cell power supply trunks 2006 to 2008 are provided. The inter-cell wirings 2001 and 2002 (shown with hatching) are formed in the second wiring layer. The inter-cell wiring 2003 for connecting the wiring end 2001a of the inter-cell wiring 2001 and the wiring end 2002a of the inter-cell wiring 2002 is formed using wiring of a wiring layer whose vertical direction is the priority wiring direction. Here, when the cells 2004 and 2005 are logic cells, the cells in the first wiring layer are present in the cells 2004 and 2005 because the intra-cell wiring (not shown) formed mainly in the first wiring layer exists. It is difficult to form other wiring in the inner region. Therefore, the inter-cell wiring 2003 is often formed in a third wiring layer or the like.

By the way, depending on the arrangement state of the cells, there may be a place where a logic cell is not arranged in the cell column. In this case, the in-cell power supply trunk lines of each logic cell are not connected. In such a location, a special cell (hereinafter referred to as a “gap cell”) that does not include an element such as a transistor and has only an in-cell power supply trunk on the upper and lower sides, etc. In general, the internal power supply trunk lines of the logic cells are connected to each other by connecting to the internal power supply trunk line. In the gap cell as described above, there is no wiring in the cell unlike the logic cell, so that it is easy to form a wiring in a region in the gap cell of the first wiring layer. However, in the case of the example of FIG. 43, since the intra-cell power supply trunk line 2006 formed in the first wiring layer exists between the wiring ends 2001a and 2002a, the first wiring layer has a priority wiring direction. Even in the vertical direction, it cannot be used as a wiring layer for forming the inter-cell wiring 2003 straddling the intra-cell power supply trunk line 2006.
US Pat. No. 6,091,090

  As described above, in the layout using the conventional layout device, for example, when the priority wiring direction of the wiring layer in which the in-cell power supply trunk line such as the first wiring layer is formed is set to a direction different from the cell column, Wiring that straddles the power supply trunk line in the cell cannot be placed in the same wiring layer, and the space (wiring resources) through which wiring can pass is reduced, so it is easy to cause wiring congestion, and in the worst case, wiring is impossible It has a problem that it tends to occur.

  The present invention is intended to solve the above-mentioned problem, and even when the priority wiring direction of the wiring layer in which the in-cell power supply trunk line is formed is set to a direction different from the cell column, the reduction of wiring resources is suppressed, The object is to make it easy to reduce wiring congestion.

In order to solve the above problems, the invention of claim 1
A semiconductor integrated circuit layout method for determining a layout of components of a semiconductor integrated circuit using a semiconductor integrated circuit layout apparatus,
A logic cell arrangement step of arranging a logic cell having a circuit element and a power supply trunk line in the logic cell for supplying a power supply voltage to the circuit element;
A connection cell arrangement step of arranging a connection cell having a connection power supply trunk line for connecting the power supply trunk line in the logic cell to a power source in an area where the logic cell is not arranged;
Have
The connection cell is a connection cell in which a connection power supply trunk line is provided in a second wiring layer different from the first wiring layer in which the logic cell power supply trunk line is provided.

  As a result, since there is no connection power trunk of the first wiring layer in the region where the connection cell is disposed, it is easy to arrange signal wiring and the like by setting the direction perpendicular to the power trunk as the priority wiring direction. Can be.

  According to the present invention, even when the priority wiring direction of the wiring layer in which the in-cell power supply trunk line is formed is set to a direction different from the cell row, it is possible to easily reduce the wiring congestion by suppressing the reduction of the wiring resources. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, components having similar functions are appropriately denoted by the same reference numerals and description thereof is omitted.

  Here, hereinafter, each wiring layer of the semiconductor integrated circuit is referred to as a first wiring layer, a second wiring layer, etc. in order from the side closest to the substrate, and the in-cell power supply trunk line of the logic cell including the elements constituting the logic circuit is The description will be made assuming that the in-cell power supply trunk line (connection power supply trunk line) of the gap cell (connection cell) having only the in-cell power supply trunk line described later is mainly provided in the second wiring layer while being provided in the first wiring layer (second wiring). The wiring of the layers is shown with hatching.) In addition, it is assumed that the direction of the power supply trunk line in the cell is the same direction as the cell row, and the priority wiring direction of the first wiring layer is a direction perpendicular to the cell row.

  Note that the arrangement of cells and wirings in the semiconductor integrated circuit as described below is performed by, for example, a layout apparatus in which software is incorporated in a computer. In addition, an actual semiconductor integrated circuit is manufactured based on information such as cell arrangement information indicating the arrangement of circuit components and wiring arrangement information indicating a wiring pattern, and is generated directly by the layout apparatus as described above. In the following, for the sake of convenience, a wiring pattern and the like produced based on such information will be schematically illustrated and described.

Embodiment 1 of the Invention
In the semiconductor integrated circuit layout method according to the first embodiment, for example, the steps shown in FIG. 1 and the following are executed by a layout apparatus or the like.

  (S101) First, a floor plan process is performed for determining the logic cell arrangement region, the arrangement of the main power supply wiring, and the like on the semiconductor substrate. That is, for example, when the specifications of a semiconductor integrated circuit are determined, first, an area necessary for arranging a logic cell is secured, and the width of the main power supply wiring and the power consumption determined for the logic cell arrangement area are satisfied. Placement is determined.

  (S102) In the determined logic cell arrangement region, for example, as shown in FIG. 2, logic cells 1001 having in-cell power supply trunk lines 1001a and 1001b of the first wiring layer are arranged on the semiconductor substrate 1000, respectively. The in-cell power supply trunk lines 1001a and 1001b are set, for example, in the cell row direction (horizontal direction in the figure), and one is used for the power supply potential and the other is used for the ground potential.

  (S103) As shown in FIG. 3, gap cells 1002 having in-cell power supply trunks 1002a and 1002b are arranged in an area where the logic cell 1001 is not arranged. That is, for example, in the layout design by the layout device, when the logic cell is arranged based on the circuit information, there is usually a place where the logic cell 1001 is not arranged in the cell column. In such a region, the gap cell 1002 is arranged as described above.

  Specifically, for example, as shown in FIGS. 4 and 5 (cross section AA in FIG. 4), the in-cell power supply trunk lines 1002a and 1002b of the gap cell 1002 have a cell frame 1002c (shown in FIG. 4). (Indicated by the alternate long and short dash line in FIG. 5). Vias 1002d connected to the in-cell power supply trunk lines 1001a and 1001b of the adjacent logic cell 1001 are formed at the ends of the in-cell power supply trunk lines 1002a and 1002b. 1002a etc. are connected continuously in the cell row direction.

  In-cell power supply trunks 1002a and 1002b of the gap cell 1002 are formed in the second wiring layer. That is, the in-cell power supply trunk line is not formed in the first wiring layer.

  (S104) The arrangement of inter-cell wiring such as signal wiring between the logic cells 1001 is determined. At this time, since the in-cell power supply trunk line is not formed in the first wiring layer in the region where the gap cell 1002 is disposed, the wiring in the direction perpendicular to the cell column, specifically, for example, FIG. It becomes possible to arrange the signal wiring 1003 as shown in FIG. Therefore, it is possible to easily arrange appropriate wiring quickly by effectively using the wiring resources in the priority wiring direction perpendicular to the cell row in the first wiring layer.

  In this case, the area of the semiconductor chip where the gap cells need to be arranged may be about several tens of the total area of the areas where the logic cells are arranged. Therefore, by using the gap cell 1002 as described above, it is possible to ease wiring congestion by utilizing the wiring resources of the first wiring layer.

(Modification of gap cell 1002)
In order to connect the in-cell power supply trunk lines 1001a and 1001b of the logic cell 1001 and the in-cell power supply trunk lines 1002a and 1002b of the gap cell 1002, as shown in FIG. In addition, a gap cell 1002 having in-cell power supply trunk lines 1001a ′ and 1001b ′ located on the extension of the in-cell power supply trunk lines 1001a and 1001b in the logic cell 1001 may be used. As described above, the wiring resources of the first wiring layer that can be secured when the in-cell power supply trunk lines 1001a ′ and 1001b ′ of the first wiring layer are provided in the cell frame 1002c (that is, in the priority wiring direction perpendicular to the cell row). The wiring resource) is smaller than that of the gap cell 1002 as shown in FIG. 5, but the gap cell 1002 as shown in FIG. 7 can be used when the wiring congestion level is low.

  Also, as shown in FIGS. 8 and 9, gap cells 1004 and 1005 having vias 1002d only on one side and gap cells 1006 without vias as shown in FIG. As shown in FIG. 12, the in-cell power trunks 1002a and 1002b of the second wiring layer may be continuous. That is, the size of the area where the logic cell is not arranged in the cell column generated after the arrangement of the logic cell is not always constant, and in some cases, the logic cell may not be arranged in a large area. In addition, it is easy to secure more wiring resources (in the priority wiring direction) of the first wiring layer by arranging a plurality of gap cells side by side as in the case where a general gap cell is arranged. Can be.

  Further, for example, as shown in FIGS. 13 to 16, the gap cells 1002, 1004, 1005, and vias 1002 d between the cell power trunks 1001 a, 1001 b, 1001 a ′, 1001 b ′ and the semiconductor substrate 1000, A similar substrate contact 1002e may be formed. By forming such a substrate contact 1002e, a power supply potential can be applied to the semiconductor substrate 1000. Therefore, the possibility that a transistor formed in a nearby region causes a latch-up phenomenon can be easily reduced. .

<< Embodiment 2 of the Invention >>
The gap cell 1006 (FIG. 10) having no via may be used to automatically connect the logic cell 1001 to the in-cell power supply trunk lines 1001a and 1001b. That is, for example, as shown in FIG. 17, after the gap cell placement step (S103) of FIG. 1 is performed, the inter-cell power supply wiring connection process (S201) automatically or in accordance with a designer's instruction or the like. As a result, the extension of the in-cell power supply trunk lines 1001a and 1002a, the addition of the in-cell power supply trunk line 1001a ′, the addition of the via 1002d, and the like may be performed. Further, the via 1002d may be added later using the gap cell 1002 in which the in-cell main power line 1002a and the like extend outside the cell frame 1002c. Further, the addition of the substrate contact 1002e may be performed later.

<< Embodiment 3 of the Invention >>
The wiring congestion degree of the inter-cell wiring connecting the logic cells is not uniform in the entire semiconductor chip, and there are high and low wiring congestion parts depending on the arrangement state of the logic cells. In a place where the degree of wiring congestion is low, there is a high possibility that sufficient wiring resources are already secured. Therefore, priority is given to the first wiring layer by using a gap cell having an in-cell power supply trunk in the second wiring layer. There is little need to secure wiring resources in the wiring direction. Therefore, a gap cell having an in-cell power supply trunk line may be arranged in the second wiring layer as described above only in a portion where the wiring congestion degree is high.

  Specifically, as shown in FIG. 18, when the same floor plan process and logic cell placement step (S101, S102) as in the first embodiment are performed, for example, the logic cell 1001 is placed as shown in FIG. Then, the following process is performed after that.

  (S301) The layout design system or the like estimates the degree of wiring congestion in an area of a predetermined size, at least between or in the vicinity of the logic cells 1001.

  (S302) As shown in FIG. 20, in an area where the estimated wiring congestion is a predetermined level or more, a gap cell having in-cell power supply trunks 1002a and 1002b in the second wiring layer as described in the first embodiment. On the other hand, a gap cell 1007 having in-cell power supply trunks 1007a and 1007b in the first wiring layer is arranged in the other region.

  Thereafter, the same inter-cell wiring placement process (S104) as in the first embodiment is performed. However, in the area where the wiring congestion is relatively high, the first wiring layer is formed in the cell in the same manner as described in the first embodiment. Since the power supply trunk line is not formed and wiring resources in the priority wiring direction are secured, wiring congestion can be reduced. On the other hand, in the region where the degree of wiring congestion is relatively low, the in-cell power supply trunk line is formed in the first wiring layer, so that it is easy to provide a substrate contact, and the resistance to the latch-up phenomenon of the transistor can be kept high. it can.

  It should be noted that, depending on the wiring congestion level or the estimation of the wiring congestion level in a narrower region unit, as shown in FIG. 21, the in-cell power supply trunk line 1007a of the first wiring layer and the in-cell power supply of the second wiring layer A gap cell 1008 having a trunk line 1002b may also be used, so that it is possible to easily achieve both a reduction in wiring congestion and a latch-up resistance. Furthermore, the in-cell power supply trunk line is not limited to being provided on either the first or second wiring layer over the entire length, but may be switched from one to the other in the cell.

  Further, not only the estimation of the wiring congestion as described above, but after the gap cell having the in-cell power supply trunk line is once arranged in the first wiring layer and the arrangement process of the inter-cell signal wiring is performed, For example, replacement with a gap cell having an in-cell power supply trunk line in the second wiring layer may be performed in a portion where the wiring cannot be arranged. Conversely, after a gap cell having an in-cell power supply trunk line is once arranged in the second wiring layer and the inter-cell wiring arrangement process is performed, the portion where the inter-cell signal wiring is not arranged or the wiring congestion degree In the lower portion, replacement with a gap cell having an in-cell power supply trunk line in the first wiring layer may be performed.

<< Embodiment 4 of the Invention >>
When the inter-cell signal wiring based on the circuit information is formed over the entire chip after the gap cell is arranged, the wiring resources of the first wiring layer secured in the gap cell depending on the degree of wiring congestion or the like In some cases, the wiring is not formed, and there is a remaining portion of wiring resources (a portion where the inter-cell signal wiring is not formed). Usually, an insulating film is formed in a portion where such wiring resources are left over, but it is also possible to newly provide a substrate contact using the remaining wiring resources.

  For example, as shown in FIG. 22, by performing the same steps as (S101 to S104) of the first embodiment, the signal wiring 1011 is arranged in the region where the gap cell 1002 is arranged as shown in FIG. On the other hand, it is assumed that a wiring free area 1012 is formed in other areas. In this case, the gap cell is then replaced (S401). For example, as shown in FIG. 24, the gap cell 1002 has a via 1013d, a substrate contact 1013e, and a first contact at a position corresponding to the wiring empty area 1012. The gap cell 1013 having the relay wiring 1013f of the wiring layer is replaced.

  That is, since the region where the relay wiring 1013f is formed is a region where the signal wiring 1011 is not formed, the gap cell 1002 can be replaced with the gap cell 1013 as described above. Then, the in-cell power supply main line 1002a is connected to the semiconductor substrate 1000 through the via 1013d, the relay wiring 1013f, and the substrate contact 1013e.

  As described above, for example, gap cells having the vias 1013d and the like are prepared in advance at various positions, and the most suitable one corresponding to the arrangement of the wiring vacant areas is selected and replaced. While securing wiring resources in the priority wiring direction and reducing wiring congestion, it is possible to reduce the possibility of latch-up phenomenon by providing many substrate contacts.

<< Embodiment 5 of the Invention >>
Instead of replacing the gap cell 1002 with the gap cell 1013 as in the fourth embodiment (S401), by adding a substrate contact (S501) as shown in FIG. 25, as shown in FIG. A via 1013d, a substrate contact 1013e, and a relay wiring 1013f may be added to the gap cell 1002. The semiconductor integrated circuit itself finally manufactured in this way is the same as that in the fourth embodiment, but it is not necessary to prepare a plurality of gap cells having different positions and numbers of substrate contacts or the like in advance.

Embodiment 6 of the Invention
Even if the gap cells are not arranged in all the regions between the logic cells, the power supply wirings of the second wiring layer may be directly arranged so that the in-cell power supply trunk lines of the respective logic cells are connected to each other.

  For example, as shown in FIG. 27, after the same floor plan process and logic cell arrangement process (S101, S102) as in the first embodiment are performed, the following process is performed.

  (S601) As shown in FIG. 28, when two logic cells 1001 and 1001 are arranged apart from each other, the gap cell as described in the first embodiment is provided only in the area adjacent to each of the logic cells 1001 and 1001. 1004 and 1004 (FIG. 8) are arranged. The gap cells 1004 and 1004 may have different widths as long as the total width is shorter than the distance between the logic cells 1001 and 1001. Here, the main power supply trunk lines 1101 and 1102 of the first wiring layer for supplying a power supply voltage to each logic cell 1001 are also drawn in FIG.

(S602) As shown in FIG. 29, inter-cell power supply wirings 1103 and 1104 for connecting the in-cell power supply trunk lines 1002a and 1002b of the gap cells 1004 are arranged. These inter-cell power supply wires 1103 and 1104 are arranged in the same second wiring layer in response to the intra-cell power supply trunk lines 1002a and 1002b of the gap cell 1004 being arranged in the second wiring layer. That is, the inter-cell power supply wires 1103 and 1104 are also automatically arranged in the second wiring layer by arranging the gap cell 1002 having the in-cell power supply trunk lines 1002a and 1002b in the second wiring layer in (S601). . (Note that the inter-cell power supply wirings 1103 and 1104 and the main power supply trunk lines 1101 and 1102 are connected by vias 1101a and 1102a, respectively, as necessary.)
Therefore, even when the main power trunks 1101 and 1102 of the first wiring layer are arranged between the logic cells 1001 and 1001, the inter-cell power wirings 1103 and 1104 are arranged so as to straddle them. As shown in FIG. 30, the signal wiring 1003 in the direction perpendicular to the cell column can be arranged by the subsequent inter-cell signal wiring processing step (S104).

<< Embodiment 7 of the Invention >>
The semiconductor integrated circuit is verified at the circuit design stage, and it is confirmed that it operates properly. However, at that time, the length of the signal wiring and parasitic capacitance are not taken into consideration, so the actually manufactured semiconductor Timing errors can occur in integrated circuits. Therefore, for critical paths that have little timing margin at the circuit design stage, the signal wiring is connected in the shortest path in advance or the detour is reduced to reduce the signal propagation delay, It is possible to reduce the possibility that a cell or wiring needs to be re-laid out. Specifically, for example, the steps shown in FIG. 31 and the following are performed.

  (S701) First, as is normally done in the circuit design stage, the timing verification confirms the operation within a range where the arrangement of signal wirings and the like are not taken into consideration.

  (S702) A critical path is obtained based on the delay time of each path obtained during the timing verification.

  (S101) (S102) The same floor plan process and logic cell arrangement process as described in the first embodiment are performed.

  (S703) If the critical path obtained in the above (S702) is, for example, a signal line that connects between the logic cells 1201 and 1202 shown in FIG. The gap cells 1002 and 1008 in which one or both in-cell power supply trunks as described in the first and fourth embodiments are formed in the second wiring layer are arranged as shown in FIG. Note that only the gap cell 1002 (both in-cell power supply trunks are the second wiring layer) may be arranged, or the gap cell 1002 and the like may be arranged in other empty areas. From the viewpoint of preventing the latch-up phenomenon, it is preferable that the number of in-cell power supply trunk lines 1002a and the like in the second wiring layer is small.

  (S704) As shown in FIG. 34, the inter-cell power supply wires 1203 and 1204 of the first wiring layer are arranged in a region where the logic cell 1201, the gap cell 1002, and the like are not arranged. Instead of performing such an inter-cell power supply wiring arrangement process, a gap cell 1007 having the in-cell power supply trunk lines 1007a and 1007b in the first wiring layer may be arranged in (S703). .

  (S104) As described in the first embodiment, the arrangement of inter-cell lines such as signal lines between the logic cells including the logic cells 1201 and 1202, for example, the signal lines 1205 and 1206 shown in FIG. 35 is determined. . The signal wiring 1205 is disposed in the second wiring layer, while the signal wiring 1206 is disposed in the first wiring layer. That is, in the region where the gap cells 1002 and 1008 are arranged, the wiring in the direction perpendicular to the cell row can be arranged in the first wiring layer, so that the signal wiring is automatically arranged in the shortest path. (Or increase the likelihood of being placed).

  The arrangement of the signal wiring as described above is not limited to the critical path obtained based on the timing verification as in (S702) above, but together with or instead of these, for example, a clock It may be performed for a signal or the like where timing is generally important, such as a signal path. Further, it may be automatically performed on a path including “clock” or “clk” in the signal name, or may be performed on a path specified by a designer or a design apparatus. May be.

  Further, instead of or together with the arrangement of the gap cell 1002 or the like as in (S703), the arrangement of the gap cell 1002 or the like according to an instruction from the designer or the like may be performed.

  Further, in (S104), the wiring for the critical path obtained in (S702) may be preferentially arranged so that the signal wiring as described above is more reliably arranged. Further, for example, a designer or the like may be able to specify the wiring arrangement itself for a signal path having a small timing margin.

  Furthermore, not only the critical path but also a similar process is performed for a path having a delay margin that is smaller than a predetermined value or relatively smaller than other paths, that is, a path with a small timing margin. Good.

<< Embodiment 8 of the Invention >>
Even after the layout of logic cells and signal wirings is made by the above-described embodiments and conventionally known layout devices and methods, even when timing errors are confirmed by timing verification considering the arrangement of signal wirings, For example, the timing can be easily improved by arranging the gap cell having the in-cell power supply trunk line in the second wiring layer as shown in FIG.

  (S801) A circuit operation simulation considering parasitic capacitance according to the arrangement of signal wirings is performed, timing verification is performed, and a path in which a timing error occurs, for example, by signal wirings 1301 and 1302 shown in FIG. A path between the connected logic cells 1201 and 1202 is detected.

  (S802) On the path where the detected path is the shortest, gap cells 1002 and 1008 in which one or both of the in-cell power supply trunk lines are formed in the second wiring layer are arranged as shown in FIG.

  (S803) The inter-cell power supply wirings 1203 and 1204 are corrected so as to correspond to the arrangement of the gap cells 1002 and 1008. Specifically, for example, the portions where the in-cell power supply trunk lines 1002a and 1002b of the gap cells 1002 and 1008 are formed may be removed. Note that the inter-cell power supply wiring may be rearranged again. Further, when the gap cell 1007 having the in-cell power supply trunk lines 1007a and 1007b is arranged in the first wiring layer in order to form the inter-cell power supply wiring, the gap cell 1007 is simply opened in the above (S802). It is only necessary to replace the cells 1002 and 1008, and there is no need to modify the inter-cell power supply wiring.

  (S804) When the signal wiring between the logic cells 1201 and 1202 is rearranged, in the region where the gap cells 1002 and 1008 are arranged, the wiring in the direction perpendicular to the cell row can be arranged in the first wiring layer. Therefore, the signal wiring of the shortest path is automatically arranged. Specifically, for example, as shown in FIG. 39, the signal wiring 1311 of the second wiring layer and the signal wiring 1312 of the first wiring layer are arranged.

<< Ninth Embodiment of the Invention >>
For example, as shown in FIG. 40, when a gap cell having an in-cell power supply main line of the second wiring layer is arranged and a timing error occurs even when the signal wiring of the shortest path is arranged as in each of the above embodiments. Thus, the timing can be improved by replacing the logic cell on the signal output side with a logic cell having a large driving force.

  (S801) First, as described in the eighth embodiment, timing verification is performed in consideration of parasitic capacitance and the like according to the arrangement of signal wirings.

  (S901) By the timing verification, as shown in FIG. 41, for example, a path between the logic cells 1201 and 1202 connected by the signal wirings 1205 and 1206 is detected, and adjacent to the logic cell 1201 on the signal output side. When the gap cell 1008 is provided, the logic cell 1201 and the gap cell 1008 are replaced with the logic cell 1401 as shown in FIG. 42, for example. That is, by replacing the logic cell 1401 with a driving capability larger than that of the logic cell 1201 and having the second-layer intra-cell power supply trunk line, the delay of the propagated signal is reduced.

  (S902) If necessary, the positions of the inter-cell power supply wirings 1203 and 1204 and the signal wiring 1205 output from the logic cell 1401 are corrected.

  As described above, if the cell area of the logic cell 1401 having a driving capability larger than that of the logic cell 1201 is smaller than the total of the logic cell 1201 and the gap cell 1008, the arrangement of other logic cells and wirings is greatly changed. Therefore, in many cases, the drive capability can be easily increased to improve the timing of signal propagation.

  In the above example, the in-cell power supply trunk of the logic cell is provided in the first wiring layer, while the in-cell power supply trunk of the gap cell is provided in the first or second wiring layer, and the priority wiring of the first wiring layer is provided. The direction has been described as a direction perpendicular to the cell column and the in-cell power supply trunk line. However, if a gap cell having an in-cell power supply trunk line is used in a wiring layer different from the in-cell power supply trunk line in at least one of the logic cells, the logic cell is used. Thus, it is possible to easily arrange the signal wiring and the like with the direction perpendicular to the in-cell power supply trunk line as the priority wiring direction. However, from the viewpoint of preventing the latch-up phenomenon, it is preferable to assign the wiring layer so that the possibility of increasing the power supply wiring and the substrate contact closest to the semiconductor substrate is increased.

  According to the semiconductor integrated circuit layout method of the present invention, even when the priority wiring direction of the wiring layer in which the in-cell power supply trunk line is formed is set to a direction different from the cell row, the reduction of wiring resources is suppressed and the wiring congestion is reduced. This is useful as a layout method using a layout device that determines the arrangement of cells and wirings.

3 is a flowchart illustrating a layout method according to the first embodiment. 2 is a plan view showing a state in which logic cells 1001 are arranged. FIG. It is a top view which shows the state by which the clearance cell 1002 is arrange | positioned similarly. FIG. 6 is a plan view showing a specific configuration of the gap cell 1002. It is AA sectional drawing of FIG. FIG. 6 is a plan view showing a state where signal wirings 1003 are arranged. It is sectional drawing which shows the modification of a clearance gap cell. It is sectional drawing which shows the other modification of a clearance gap cell. It is sectional drawing which shows the other modification of a clearance gap cell. It is sectional drawing which shows the further another modification of a clearance gap cell. It is sectional drawing which shows the example of the combination of the modification of a clearance gap cell. It is sectional drawing which shows the other example of the combination of the modification of a clearance gap cell. It is sectional drawing which shows the other modification of a clearance gap cell. It is sectional drawing which shows the other modification of a clearance gap cell. It is sectional drawing which shows the other modification of a clearance gap cell. It is sectional drawing which shows the other modification of a clearance gap cell. 10 is a flowchart illustrating a layout method according to the second embodiment. 10 is a flowchart illustrating a layout method according to the third embodiment. 2 is a plan view showing a state in which logic cells 1001 are arranged. FIG. FIG. 6 is a plan view showing a state where gap cells 1002 and the like are arranged. FIG. 6 is a plan view showing a state where gap cells 1008 and the like are arranged. 10 is a flowchart illustrating a layout method according to the fourth embodiment. FIG. 6 is a cross-sectional view showing a state where signal wirings 1011 are arranged. It is sectional drawing which shows the structure of the clearance gap cell 1013 replaced similarly. 10 is a flowchart illustrating a layout method according to a fifth embodiment. FIG. 6 is a cross-sectional view showing a state where a substrate contact 1013e and the like are added. 14 is a flowchart illustrating a layout method according to the sixth embodiment. It is a top view showing the state where gap cell 1004 is arranged similarly. FIG. 3 is a plan view showing a state where inter-cell power supply wirings 1103 and the like are arranged. FIG. 6 is a plan view showing a state where signal wirings 1003 are arranged. 18 is a flowchart illustrating a layout method according to the seventh embodiment. 2 is a plan view showing the arrangement of critical path logic cells 1201 and the like. FIG. FIG. 6 is a plan view showing a state where gap cells 1002 and the like are arranged. FIG. 6 is a plan view showing a state where inter-cell power supply wiring 1203 and the like are arranged. FIG. 6 is a plan view showing a state where signal wirings 1205 and the like are arranged. 19 is a flowchart illustrating a layout method according to an eighth embodiment. FIG. 6 is a plan view showing an example of arrangement of signal wirings in which a timing error occurs. It is a top view which shows the state by which the clearance cell 1008 is arrange | positioned similarly. FIG. 6 is a plan view showing a state in which signal wirings 1311 and the like are arranged. 10 is a flowchart illustrating a layout method according to the ninth embodiment. FIG. 6 is a plan view showing an example of arrangement of signal wirings in which a timing error occurs. FIG. 11 is a plan view showing an example in which the logic cell 1401 having a large driving capability is replaced. It is a top view which shows the example of the layout by the conventional layout method.

Explanation of symbols

1000 Semiconductor substrate 1001 Logic cell 1001a In-cell power supply trunk line 1001a 'In-cell power supply trunk line 1001b In-cell power supply trunk line 1001b' In-cell power supply trunk line 1002 Gap cell 1002a In-cell power supply trunk line 1002b In-cell power supply trunk line 1002c Cell frame 1002d Contact 1002e Substrate 1003e Signal wiring 1004 Gap cell 1005 Gap cell 1006 Gap cell 1007 Gap cell 1007a In-cell power supply trunk line 1007b In-cell power supply trunk line 1008 Gap cell 1011 Signal wiring 1012 Region 1013 Gap cell 1013d Via 1013e Substrate contact 1013f Main power line 1101 1101 Main power supply main line 1102a Via 1103 Inter-cell power supply wiring 1104 Inter-cell power supply wiring 1201 Logic cell 202 logic cell 1203 inter-cell power wiring 1203 cell between the power lines 1204 cells between the power lines 1205 signal lines 1206 signal lines 1301 signal lines 1302 signal lines 1311 signal lines 1312 signal lines 1401 logic cells

Claims (25)

A semiconductor integrated circuit layout method for determining a layout of components of a semiconductor integrated circuit using a semiconductor integrated circuit layout apparatus,
A logic cell arrangement step of arranging a logic cell having a circuit element and a power supply trunk line in the logic cell for supplying a power supply voltage to the circuit element;
A connection cell arrangement step of arranging a connection cell having a connection power supply trunk line for connecting the power supply trunk line in the logic cell to a power source in an area where the logic cell is not arranged;
Have
A layout method of a semiconductor integrated circuit, wherein the connection cell is a connection cell in which a connection power supply trunk line is provided in a second wiring layer different from the first wiring layer in which the power supply trunk line in the logic cell is provided. A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
A layout method of a semiconductor integrated circuit, wherein the first wiring layer is a wiring layer closest to a semiconductor substrate. A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
A layout method of a semiconductor integrated circuit, wherein in the connection cell arrangement step, the connection cells are arranged in all regions where the logic cells are not arranged. A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
In the connection cell arrangement step, the connection cell is arranged in a part of a region where the logic cell is not arranged,
Further, in the area where neither the logic cell nor the connection cell is arranged, the inter-cell power supply wiring for connecting the power supply trunk lines in the logic cell, between the connection power supply trunk lines, or between the power supply trunk line in the logic cell and the connection power supply trunk line is arranged. A method for laying out a semiconductor integrated circuit, comprising the step of arranging inter-cell power supply wiring. A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
The semiconductor integrated circuit layout method further comprises an inter-cell signal wiring arrangement step for determining an arrangement of signal wirings connected between the logic cells after the logic cell arrangement step and the connection cell arrangement step. . A semiconductor integrated circuit layout method according to claim 5, comprising:
A layout method of a semiconductor integrated circuit, wherein the inter-cell signal wiring arrangement step determines the arrangement of the signal wiring by setting a direction perpendicular to the power supply main line in the logic cell as a priority wiring direction of the first wiring layer. . A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
The connection cell has a power supply main line connection via for connecting the connection power supply main line and an in-logic cell power supply main line of a logic cell adjacent to the connection cell at at least one end of the connection power supply main line. A method for laying out a semiconductor integrated circuit. A method for laying out a semiconductor integrated circuit according to claim 7, comprising:
The first wiring layer is a wiring layer closest to the semiconductor substrate;
The layout method of a semiconductor integrated circuit, wherein the connection cell further has a substrate contact for connecting the power trunk line in the logic cell and the semiconductor substrate at a position corresponding to the power trunk connection via. A method for laying out a semiconductor integrated circuit according to claim 7, comprising:
A layout method of a semiconductor integrated circuit, wherein both end portions of the connection power supply main line and the power supply main line connection via in the connection cell are located inside a cell frame showing a standard outline of the connection cell. A method for laying out a semiconductor integrated circuit according to claim 7, comprising:
A layout method of a semiconductor integrated circuit, wherein both ends of the connection power supply main line and the power supply main line connection via in the connection cell are located outside a cell frame showing a standard outline of the connection cell. A method for laying out a semiconductor integrated circuit according to claim 7, comprising:
The connection cell placement step includes
A first connection cell having a power supply main line connection via that connects the connection power supply main line and an in-logic power supply main line of a logic cell adjacent to the connection cell at one end of the connection power supply main line;
A second connection cell located on the other side of the first connection cell and having a power supply main line connection via at the other end of the connection power supply main line;
One or more third connection cells located between the first and second connection cells and having a connection power supply trunk connecting the connection power supply trunks of the first and second connection cells;
A method for laying out a semiconductor integrated circuit, characterized by comprising: A semiconductor integrated circuit layout method according to claim 11, comprising:
The layout of the semiconductor integrated circuit, wherein the end of the connection power supply main line and the power supply main line connection via in the first and second connection cells are located on the inner side of a cell frame showing a standard outline of the connection cell. Method. A semiconductor integrated circuit layout method according to claim 11, comprising:
The layout of the semiconductor integrated circuit, wherein the end of the connection power supply main line and the power supply main line connection via in the first and second connection cells are located outside the cell frame showing the standard outline of the connection cell. Method. A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
Furthermore, it has a wiring congestion degree calculation step for obtaining the wiring congestion degree of the signal wiring connected between the logic cells,
A layout method of a semiconductor integrated circuit, wherein the connection cell placement step arranges the connection cell in a region where the wiring congestion degree is not less than a predetermined value in a region where the logic cell is not disposed. A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
Furthermore, it has a wiring congestion degree calculation step for obtaining the wiring congestion degree of the signal wiring connected between the logic cells,
In the connection cell placement step, the connection power supply line of the first wiring layer and the connection power supply of the second wiring layer are arranged in a region where the wiring congestion degree is not less than a predetermined value in a region where the logic cell is not disposed. A layout method of a semiconductor integrated circuit, wherein a connection cell having a main line is arranged. The semiconductor integrated circuit layout method according to claim 2, further comprising:
After the logic cell placement step and the connection cell placement step, an inter-cell signal wire placement step for determining the placement of signal wires connected between the logic cells;
Instead of the connection cell arranged in the connection cell arrangement step, the relay wiring of the first wiring layer, the connection power supply trunk line and the relay wiring are connected to a region where the signal wiring in the connection cell is not arranged. A connection cell replacement step of disposing a connection cell having a relay via and a substrate contact connecting the relay wiring and the semiconductor substrate;
A method for laying out a semiconductor integrated circuit, comprising: The semiconductor integrated circuit layout method according to claim 2, further comprising:
After the logic cell placement step and the connection cell placement step, an inter-cell signal wire placement step for determining the placement of signal wires connected between the logic cells;
The relay wiring of the first wiring layer, the relay via for connecting the connection power supply trunk line and the relay wiring to the region where the signal wiring is not arranged in the connection cell arranged in the connection cell arrangement step, and the relay wiring A substrate contact adding step for adding and arranging a substrate contact for connecting the semiconductor substrate and the semiconductor substrate;
A method for laying out a semiconductor integrated circuit, comprising: A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
The connection cell placement step arranges the connection cells in regions adjacent to the logic cells on both ends of the region where the logic cells are not disposed,
further,
A method for laying out a semiconductor integrated circuit, comprising: an inter-cell power supply wiring arrangement step for arranging an inter-cell power supply wiring of a second wiring layer for connecting the connection power supply trunk lines of each connection cell to each other. A method for laying out a semiconductor integrated circuit according to claim 1, comprising:
Furthermore, it has a timing verification step for performing timing verification of circuit operation,
A layout method of a semiconductor integrated circuit, wherein the connection cell arrangement step arranges the connection cell on a shortest path of a signal wiring of a path having a small timing margin. The semiconductor integrated circuit layout method according to claim 1, further comprising:
An inter-cell signal wiring arrangement step for determining an arrangement of signal wirings connected between the logic cells;
A timing verification step for performing timing verification of circuit operation in consideration of the influence of the arrangement of the logic cell and the signal wiring;
Have
The connection cell placement step arranges the connection cell on the shortest path of the signal wiring of the path whose timing required by the timing verification does not satisfy a predetermined condition,
The inter-cell signal wiring arrangement step further comprises rearranging the signal wiring, wherein the semiconductor integrated circuit layout method is characterized. The semiconductor integrated circuit layout method according to claim 1, further comprising:
An inter-cell signal wiring arrangement step for determining an arrangement of signal wirings connected between the logic cells;
A timing verification step for performing timing verification of circuit operation in consideration of the influence of the arrangement of the logic cell and the signal wiring;
Instead of a logic cell that outputs a signal to a signal wiring of a path whose timing required by the timing verification does not satisfy a predetermined condition, and a connection cell adjacent to the logic cell, the driving capacity is larger than the logic cell, and A logic cell replacement step of arranging a logic cell having a power trunk in the logic cell of the second wiring layer;
A method for laying out a semiconductor integrated circuit, comprising: A semiconductor integrated circuit layout method for determining a layout of components of a semiconductor integrated circuit using a semiconductor integrated circuit layout apparatus,
A first cell placement step of placing a first cell having an in-cell power trunk in a first wiring layer;
A second cell placement step of placing a second cell having an in-cell power supply trunk on a second wiring layer different from the first wiring layer;
A method for laying out a semiconductor integrated circuit, comprising: A semiconductor integrated circuit layout method for determining a layout of components of a semiconductor integrated circuit using a semiconductor integrated circuit layout apparatus,
A cell placement step of placing a cell having a power supply wiring;
A layout method of a semiconductor integrated circuit, wherein the power supply wiring of the cell extends to the outside of a cell frame showing a standard external shape of the cell. A method for laying out a semiconductor integrated circuit according to claim 23, comprising:
A layout method for a semiconductor integrated circuit, wherein the cell further includes a connection via for connecting the power supply wiring and a power supply wiring of a wiring layer different from the power supply wiring. A semiconductor integrated circuit in which circuit elements, power supply wirings, and signal wirings are formed on a semiconductor substrate,
A first power wiring formed in the first wiring layer and supplying a power voltage to the circuit element;
A second power line formed in a second wiring layer different from the first wiring layer and connecting the first power line to a power source;
A semiconductor integrated circuit, comprising: a signal wiring formed in the first wiring layer and extending in a direction intersecting with the second power supply wiring.

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