JP5260166B2 - Semiconductor integrated circuit and layout method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and a layout method of a semiconductor integrated circuit, in which a power supply line pattern is reinforced without disturbing signal wiring in an upper layer. <P>SOLUTION: The layout method of a semiconductor integrated circuit includes: a base layer in which a logic device is prepared; and an upper layer prepared on the base layer. The method also includes steps of: laying out two or more power supply lines prolonged on the upper layer and generating power supply line data, and laying out the logic device on the base layer and generating logic device data; and a laying out a conductive pattern for power supply reinforcement based on the power supply line data and the logic device data and generating pattern data for power supply reinforcement. The step of generating the pattern data for power supply reinforcement includes a step of laying out the pattern for power supply reinforcement in a region in which the logic device is not laid out in the base layer so that the two or more prolonged power supply line patterns are connected together. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit layout method.

  In a semiconductor device, a logic element such as a transistor, a power supply wiring for supplying a power supply potential to the logic element, and a signal wiring connected to the logic element for exchanging signals are provided on a semiconductor substrate. It is done. Usually, the logic element is provided in the base layer. The underlayer is a well and diffusion layer formed on the surface of the semiconductor substrate and a layer formed thereon. The power supply wiring and the signal wiring are provided in the upper layer. The upper layer is a layer formed on the lower layer and is composed of a wiring layer.

  When designing the layout of a semiconductor integrated circuit, first, the power supply wiring width is determined by considering the current value and voltage drop value flowing through the power supply wiring by simulation, and the power supply wiring is laid out. Thereafter, the logic elements and signal wirings are laid out. However, depending on the wiring situation in which the signal wiring is laid out, the value of the current flowing through the power supply wiring and the potential drop due to the signal wiring may be larger than the initial simulation, and the layout of the power supply wiring may be necessary.

  Therefore, the layout of the power supply wiring may be corrected after the logic elements and signal wiring are laid out.

  A technique relating to the correction of the layout of the power supply wiring is described in Japanese Patent Application Laid-Open No. 2004-186417. The semiconductor integrated circuit of Patent Document 1 includes a plurality of cell rows in which cells having unit cell lengths are arranged on a semiconductor substrate, two types of potential wiring patterns that give different potentials from the outside to the inside of the device, Two types of potential wirings arranged extending from two types of potential wiring patterns in a direction parallel to the cell row, and the two types of potential wirings are alternately arranged at intervals of the unit cell length, Each cell is connected to the two types of potential wiring. This semiconductor integrated circuit is characterized by including a power supply reinforcing filler cell for connecting adjacent potential wirings of the same type. It is described that this power reinforcing filler cell is provided with aluminum wiring. Further, it is described that the power supply line reinforcing filler cell has Al wiring, so that the Al occupation ratio of each placement wiring layer can be increased after the placement wiring.

JP 2004-186417 A

  Patent Document 1 has a description that the Al occupancy rate of each arranged wiring layer can be increased by a power source reinforcing filler cell. Therefore, it is considered that the aluminum wiring of the power reinforcing filler cell is provided in the arrangement wiring layer. The placement wiring layer is considered to be a layer in which signal wiring is formed. That is, it is considered that the placement and wiring layer corresponds to the upper layer, and a pattern for strengthening the power supply wiring (power supply strengthening pattern) is formed in the upper layer.

  When the power reinforcing pattern is provided in the upper layer, the space where the signal wiring is disposed is limited. Due to the limitation of the arrangement space, the spatial wiring resources of the signal wiring are reduced. Further, in order to cross the signal wiring and the power reinforcing pattern, it is necessary to take a countermeasure such as detouring one pattern to another layer. In order to take such a countermeasure, it is necessary to re-lay out the signal wiring, and TAT (Turn Around Time) increases.

  A method for laying out a semiconductor integrated circuit according to the present invention is a method for laying out a semiconductor integrated circuit comprising a base layer provided with a logic element and an upper layer provided on the base layer. The layout method includes a step in which a computer lays out a plurality of power supply wirings extending on an upper layer and generates power supply wiring data, and a step in which a computer lays out logic elements on a base layer and generates logic element data. And a computer laying out a conductive power enhancement pattern on the underlayer based on the power supply wiring data and the logic element data, and generating power enhancement pattern data. The step of generating the power enhancement pattern data includes the step of laying out the power enhancement pattern so that a plurality of power supply wiring patterns extending to each other are connected to a region in the underlying layer where the logic elements are not laid out. Yes.

  According to the present invention, the power supply wiring pattern initially laid out can be corrected by the power supply reinforcing pattern, and the power supply voltage supply capability is enhanced. Here, the power reinforcing pattern is provided on the base layer. Therefore, there is no space restriction due to the power reinforcing pattern with respect to the signal wiring pattern formed on the upper layer. That is, the power supply wiring pattern can be strengthened without interfering with the signal wiring pattern in the upper layer.

  A semiconductor integrated circuit layout program according to the present invention is a program for causing a computer to execute the above-described semiconductor device layout method.

  A semiconductor integrated circuit layout apparatus according to the present invention is an apparatus in which the above-described semiconductor integrated circuit layout program is installed.

  A semiconductor integrated circuit according to the present invention includes a base layer provided on a semiconductor substrate and an upper layer provided on the base layer. The underlying layer is provided with a logic element and a conductive power supply enhancement pattern. On the upper layer, a plurality of power supply wiring patterns and signal wirings electrically connected to the logic elements are provided. The power reinforcing pattern is provided so as to electrically connect the plurality of power wiring patterns extending.

  ADVANTAGE OF THE INVENTION According to this invention, the layout method of a semiconductor integrated circuit and a semiconductor integrated circuit which can reinforce a power supply wiring pattern without interfering with the signal wiring pattern in an upper layer is provided.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a semiconductor integrated circuit according to the present embodiment.

  As shown in FIG. 1, the semiconductor integrated circuit includes a semiconductor substrate 1, a base layer, and an upper layer. The underlayer is formed on the semiconductor substrate 1. The upper layer is formed on the lower layer.

  The underlayer is a layer provided with logic elements. In FIG. 1, a transistor is illustrated as an example of a logic element. The transistor includes a source / drain diffusion layer 3 provided on the surface of the semiconductor substrate 1 and a gate electrode 2 formed on the semiconductor substrate 1 via a gate insulating film. The logic element (transistor) is embedded with an interlayer insulating film. A contact 4 is provided on the interlayer insulating film. The source / drain diffusion layer 3 of the transistor is connected to the upper layer through a contact 4.

  The upper layer has a structure in which a plurality of wiring layers are stacked. In the example of FIG. 1, the wiring layer M1 and the wiring layer M2 are formed in the upper layer. Each wiring layer is provided with metal wiring (M1, M2). The metal wirings M1 and M2 are filled with an insulating film. The metal wiring M1 and the metal wiring M2 are connected via vias formed in the insulating film. The metal wiring (M1, M2) is formed of, for example, aluminum or copper. The metal wiring M1 is connected to a transistor provided in the base layer via a contact 4 provided in the base layer.

  FIG. 2 is a schematic diagram showing a wiring layout in the upper layer. FIG. 2 shows an example in which four wiring layers (M1 to M4) are provided as the upper layer. In the upper layer, a power supply wiring (VDD) for supplying a power supply voltage, a ground wiring (GND), and a signal wiring for transmitting and receiving signals are provided. In FIG. 2, signal wiring is not shown. In the example of FIG. 2, the power supply wiring VDD is provided in the wiring layer M1 and the wiring layer M4. The power supply wiring VDD extends to a plurality of lines. The plurality of power supply wirings are connected to each other through vias or the like. In order to supply the power supply voltage stably (in order to strengthen the power supply), it is conceivable to reduce the interval between the power supply wirings. Further, as described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2004-186417), it is conceivable to provide a power reinforcing pattern for connecting adjacent power supply wiring patterns in the upper layer. However, if the interval between the power supply wiring patterns is reduced, the space in which the signal wiring is arranged is limited. Moreover, even if the power reinforcing pattern is provided on the upper layer, the space where the signal wiring is arranged is limited.

  Therefore, in this embodiment, a power reinforcing pattern for connecting a plurality of power supply wirings VDD is provided in the base layer.

  FIG. 3 is a schematic diagram showing a layout of the semiconductor integrated circuit of the present embodiment. In FIG. 3, the layout of the upper layer and the layout of the base layer are drawn so as to overlap each other. The base layer is provided with a power reinforcing pattern in addition to a region where a logic element is formed (logic element forming region). The power supply wiring VDD and the power reinforcing pattern are connected by a contact (not shown in FIG. 3) provided in the interlayer insulating film. Thereby, the power supply wirings VDD extending to a plurality of upper layers are electrically connected by the power reinforcing pattern. Here, the power reinforcing pattern intersects with the ground wiring GND and the signal wiring. However, since the ground wiring GND and the signal wiring are provided in the upper layer, there is no short circuit with the power reinforcing pattern.

  As shown in FIG. 3, if the power reinforcing pattern is arranged in the base layer, the power voltage supply capability can be enhanced without limiting the space in which the signal wiring pattern is arranged.

  The material for forming the power reinforcing pattern is not particularly limited as long as it is conductive. Specific examples of the material for the power reinforcing pattern include a metal film such as copper or aluminum, a polysilicon film, and a diffusion layer or well into which impurity ions are implanted. The power reinforcing pattern may be made of the same material as the gate electrode included in the transistor. If the power reinforcing pattern and the gate electrode are made of the same material, there is no need to add a process for providing the power reinforcing pattern during manufacturing.

  Further, the power enhancement pattern can be a metal film such as an ohmic electrode such as a source or drain electrode. When the ohmic electrode material is used for the power reinforcing pattern, it is not necessary to add a new process for forming the power reinforcing pattern, as in the case of using the gate electrode material for the power reinforcing pattern.

  Subsequently, the layout device of the semiconductor integrated circuit according to the present embodiment will be described. A semiconductor integrated circuit layout apparatus is realized by a ROM (Read Only Memory) that stores a layout program of a semiconductor integrated circuit and a CPU that executes the layout program.

  FIG. 4 is a block diagram schematically showing a functional configuration of the layout device of the semiconductor integrated circuit. The semiconductor integrated circuit layout device includes a logic element placement unit 11, a power enhancement cell placement unit 12, a VDD / GND placement unit 13, and a signal wiring placement unit 14.

  The operation of the semiconductor integrated circuit layout device will be described with reference to FIGS. 5 and 6A to 6C. FIG. 5 is a flowchart showing the operation of the semiconductor integrated circuit layout device.

Step S10: Generation of power supply data / GND data First, the VDD / GND placement unit 13 determines the position of the power supply wiring based on the setting data read via an input device (mouse, keyboard, etc.) (not shown) (layout) ) Thereby, power supply wiring data is generated. Similarly, the VDD / GND placement unit 13 determines the position of the ground wiring and generates GND data. FIG. 6A is a conceptual diagram showing VDD data and GND data. In the VDD data, the power supply wiring VDD is laid out so as to extend to a plurality (two). Further, via data between wiring layers is also generated and added to the power supply data / GND data.

Step S20: Arrangement of Logic Element Formation Region Subsequently, the logic element placement unit 11 determines a region where a logic element is formed based on VDD data and GND data, and generates logic element data. FIG. 6B is a conceptual diagram showing logic element data. In FIG. 6B, for convenience of explanation, the power supply wiring and the ground wiring are also drawn. Usually, the logic element is arranged between the power supply wiring VDD and the ground wiring GND. Here, the logic element includes not only a single transistor but also a functional cell such as a macro cell. Note that a gap region where no logic element is arranged is formed in the base layer.

Step S30: Arrangement of Power Reinforcement Cells Subsequently, the power enhancement cell placement unit 12 determines the position of the power enhancement pattern based on the logic element data, the VDD data, and the GND data, and the power enhancement pattern data. Is generated. FIG. 6C is a conceptual diagram showing the power enhancement pattern data. FIG. 6C also shows the positions of the power supply wiring VDD, the ground wiring GND, and the logic element formation region. As shown in FIG. 6C, the power reinforcing pattern is arranged so that a plurality of power supply wirings VDD are connected to each other in a gap region in the base layer.

Step S40: Arrangement of Signal Wiring Subsequently, the signal wiring arrangement unit 14 determines the position of the signal wiring based on the logic element data, the power supply data, and the GND data, and generates the signal wiring data. Since the signal wiring is provided in the upper layer, it is arranged regardless of the position of the power reinforcing pattern provided in the lower layer.

Step S50: Generation of Layout Data Subsequently, the layout data generation unit 15 generates layout data by combining the logic element data, power enhancement cell data, signal wiring data, power supply data, and GND data. Further, data of the contact 4 connecting the arranged power reinforcing pattern, the power supply wiring VDD, and the ground wiring GND is generated and added to the layout data. Thereby, layout data of the semiconductor integrated circuit as shown in FIG. 3 is generated. The generated layout data is used when actually manufacturing a semiconductor integrated circuit.

  As described above, according to the present embodiment, since the power reinforcing pattern is formed in the base layer, there is no space restriction when the signal wiring positions are determined. There is no need to re-layout the signal wiring in order to cross the signal wiring with the power enhancement pattern, and TAT does not increase.

  In this embodiment, the signal wiring is arranged (S40) after the step (S30) of arranging the power reinforcing pattern. However, since the signal wiring can be arranged regardless of the power reinforcing pattern, the position of the signal wiring may be determined before determining the position of the power reinforcing pattern.

  Further, in the present embodiment, it has been described on the assumption that a gap area in which no logic element is provided is generated in step S20. However, after the logic element formation region is determined, there may be no gap region for arranging the power reinforcing pattern. In such a case, as shown in FIG. 7, the logic element placement unit 11 may rearrange the logic element formation region so that a gap region for placing the power reinforcing pattern is generated. Thereby, the pattern for power supply reinforcement can be arrange | positioned reliably.

It is sectional drawing which shows a semiconductor integrated circuit typically. It is a perspective view which shows the layout of an upper layer typically. It is a top view which shows typically the layout of a semiconductor integrated circuit. It is a schematic block diagram which shows the structure of the layout apparatus of a semiconductor integrated circuit. 3 is a flowchart illustrating a layout method of a semiconductor integrated circuit. It is explanatory drawing for demonstrating the layout method of a semiconductor integrated circuit. It is explanatory drawing for demonstrating the layout method of a semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate electrode 3 Source / drain diffused layer 4 Contact 11 Logic element arrangement | positioning part 12 Power supply reinforcement cell arrangement | positioning part 13 VDD / GND arrangement | positioning part 14 Signal wiring arrangement | positioning part 15 Layout data generation part

Claims (5)

A method for laying out a semiconductor integrated circuit, comprising: a base layer provided with logic elements; and an upper layer provided on the base layer,
A computer laying out a plurality of power lines extending in the upper layer and generating power line data;
A computer laying out the logic elements on the underlayer and generating logic element data;
A computer laying out a conductive power enhancement pattern on the underlayer based on the power supply wiring data and the logic element data, and generating power enhancement pattern data;
Comprising
In the step of generating the power enhancement pattern data, the power enhancement pattern is laid out so that the plurality of power supply wiring patterns extending to the plurality of power supply wiring patterns are connected to a region of the base layer where the logic elements are not laid out. comprising the step of,
The step of generating the logic element data includes generating the logic element data such that a gap for arranging the power enhancement pattern is generated when a gap for arranging the power enhancement pattern is not generated in the underlying layer. A method for laying out a semiconductor integrated circuit, comprising re-laying out the elements . A semiconductor integrated circuit layout method according to claim 1, comprising:
Furthermore,
A computer laying out signal wiring on the upper layer and generating signal wiring data;
A method for laying out a semiconductor integrated circuit comprising: Claim 1 or for executing a layout process of a semiconductor device according to the computer 2, the semiconductor integrated circuit layout program. A layout apparatus for a semiconductor integrated circuit, comprising: a base layer provided with logic elements; and an upper layer formed on the base layer,
Laying out a plurality of power lines extending in the upper layer, and generating power line data;
Logic element placement means for laying out the logic elements on the underlying layer and generating logic element data;
Based on the power supply wiring data and the logic element data, a power enhancing pattern arranging means for laying out a conductive power enhancing pattern on the base layer and generating power enhancing pattern data;
Steps,
Comprising
The power reinforcing pattern arranging means lays out the power reinforcing pattern so that the plurality of power wirings extending to the plurality of power wirings are connected to a region of the base layer where the logic elements are not laid out.
The logic element arranging means repositions the logic element so that a gap for arranging the power enhancement pattern is generated when a gap for arranging the power enhancement pattern is not formed in the underlayer. Re- layout Layout device for semiconductor integrated circuit. A semiconductor integrated circuit layout device according to claim 4 ,
Furthermore,
A signal wiring arrangement means for laying out signal wiring on the upper layer and generating signal wiring data;
A semiconductor integrated circuit layout apparatus comprising:

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