JP5126194B2 - CMOS integrated circuit and photomask - Google Patents

Description

  The present invention relates to a CMOS integrated circuit having a multilayer wiring layer and a photomask therefor.

  Conventionally, a semiconductor integrated circuit is always required to reduce its chip size, operate at high speed, and improve the degree of integration. For this reason, development in close contact with wafer process technologies such as shortening the channel length of MOS elements, reducing the contact size, and reducing the allowance of contacts to semiconductors and conductors is constantly in progress.

  Such technological development relates to the characteristics of the elements in the chip, but the wiring part of the chip is also a major factor for reducing the size, operating at high speed, and improving the degree of integration. FIG. 5 is an explanatory view of an example of a general CMOS integrated circuit in a plan view, and shows only various circuit blocks. The CMOS integrated circuit 1 includes each block, and the block is formed according to its function. Examples include a logic area unit 200, a memory block 8, a large-scale logic block 9 such as a CPU, and the like. The logic area 200 is formed by arranging the row area 2 vertically and horizontally, and the row area 2 is formed by arranging and wiring cells having basic functions. In the row region 2, basic power supply and ground wiring patterns are formed in the vertical direction (formation region 209), and are connected to the respective row regions 2. In general, the row region portion 2 registers basic cells having various basic functions, and is automatically designed by automatic placement and routing software as disclosed in Patent Document 1 in accordance with circuit data of a desired logic function.

  In the logic region portion 200 and the row region portion 2, the area occupied by the wiring increases as the number of circuit elements increases. For this reason, the wiring is multilayered. The first layer wiring pattern is used for power supply, grounding and wiring inside the cell, and the second and higher intermediate wiring layers are used for signal wiring patterns. The main power supply and ground wiring generally use the top layer pattern. In particular, the uppermost layer can be used well for power supply and ground wiring because the film forming the wiring pattern can be thickened and the resistance value can be reduced. When the middle wiring layer in the meantime is patterned by the wafer process, a step is generated at the end of the pattern, and the flatness of the upper wiring layer is lost. For this reason, the film can be formed thick only in the uppermost layer or the layer immediately below it. Such a layer that can be formed thick is usually the fourth layer or more. When it is necessary to widen the pattern of power supply or grounding, since the resistance is small with a thick film, the width to be spread is smaller than other layers.

  Further, the wiring layers are used by limiting the wiring direction of each layer to only the horizontal direction and only the vertical direction when the CMOS integrated circuit 1 is viewed in plan. By doing so, the pattern density can be improved and the parasitic capacitance can be reduced.

FIG. 6 is a partial explanatory view of an example of the circuit configuration of such a logic area 200 as viewed in a plane. In the row region 2, many types and a large number of basic cells 4 are arranged and wired, and a power supply wiring 11 and a ground wiring 21 are formed at upper and lower ends in a plan view inside the basic cell 4.
In the row region, both the main power wiring 10 and the ground wiring 20 are formed vertically in the uppermost wiring layer, and the power wiring 11 and the ground wiring 21 in the cell in each row region are connected via the via 30. Connected.

Such a CMOS integrated circuit is designed by arranging and wiring the pattern data of the basic cells as described above, producing a photomask from this data, and producing it by using a wafer process.

  Known documents are shown below.

JP 2006-202824 A

  As described above, in the CMOS integrated circuit 1, the power source and the ground voltage are connected from the uppermost wiring layer to the lowermost layer via the via 30, and the via penetrates through the middle wiring layer and is conductive. FIG. 7 is an explanatory diagram schematically showing, in section, the power supply wiring or ground wiring in the lowermost layer and the portion connected to the power supply wiring or ground wiring formed in the uppermost layer via vias. FIG. 7A shows a cross section of the via portion, and FIG. 7B shows a wiring state in the vicinity of the via portion. In this example, four layers of multilayer wiring (M1 (lowermost layer), M2, M3, and M4 (uppermost layer)) are filled with the vias in each layer and through holes (contact holes) between them. The uppermost layer and the lowermost layer are electrically connected. Therefore, wiring with a middle wiring layer was not possible in this part. In particular, when the wiring between the upper and lower row region portions cannot be connected on the row region portion, the row region portion must be widened and wired. In addition, if a voltage drop (IR-Drop) exceeding the allowable range occurs in the power supply or grounding of the row region after arranging and wiring the cell, it is necessary to redesign. In this case, the wiring width of the power supply wiring 10 and the ground wiring 20 formed in the uppermost layer is increased, and as a result, the chip size is increased.

  The present invention has been made in view of such problems. A CMOS integrated circuit and a photomask for the same that can improve the power supply and grounding pattern, increase the wiring efficiency, reduce the chip size, and improve the operation speed. The issue is to provide.

The present invention has been made in view of the problems, and the invention of claim 1
In a CMOS integrated circuit in which a plurality of row regions are arranged vertically and horizontally, a plurality of wiring layers are provided, and interlayer wirings are connected via vias,
The power supply pattern A and the ground pattern A are formed in the vertical direction in the uppermost wiring layer having a large film thickness in the row region in the horizontal direction,
In the region where the power supply pattern A is formed in the vertical direction, the power supply pattern in the row region is separated into left and right within the formation region of the vertical power supply pattern A and is connected to the vertical power supply pattern A via each via. The vertical ground pattern B is formed in the same layer as the ground pattern of the row region portion and is directly connected to the ground pattern of the row region portion between the separated power patterns of the row region portion,
In the region where the ground pattern A is formed in the vertical direction, the ground pattern in the row region is separated into left and right within the region where the vertical ground pattern A is formed, and is connected to the vertical ground pattern A via each via. The vertical power supply pattern B is formed in the same layer as the power supply pattern of the row region portion and is directly connected to the power supply pattern of the row region portion between the ground patterns of the separated row region portion. This is a characteristic CMOS integrated circuit.

  According to a second aspect of the present invention, there is provided a CMOS integrated circuit according to the first aspect, wherein a wiring pattern of another layer is formed between regions where the left and right power supply patterns or ground patterns are formed. It is a thing.

  A third aspect of the present invention is a photomask used for forming a wiring layer of the CMOS integrated circuit according to the first or second aspect.

  Since the CMOS integrated circuit according to the present invention has the above-described configuration, the CMOS integrated circuit capable of improving the power supply and grounding patterns, increasing the degree of freedom of wiring, reducing the chip size, and improving the operation speed, and for the same It can be a photomask.

It is the partial explanatory view which showed typically the logic area | region part of an example of the CMOS integrated circuit of this invention with the plane. It is the partial explanatory view which showed typically the logic area | region part of the other example of the CMOS integrated circuit of this invention with the plane. It is the partial explanatory view which showed the wiring part of the logic area | region part based on this invention typically on the plane. It is explanatory drawing which showed the example of the connection part of the power supply pattern which concerns on this invention. It is explanatory drawing which showed typically an example of the general CMOS integrated circuit by the plane. It is the partial explanatory view which showed typically the logic area | region part of an example of a general CMOS integrated circuit with the plane. It is explanatory drawing which showed typically the wiring of the lowest layer of the example of a general CMOS integrated circuit, the wiring of the uppermost layer, and the via | veer in the cross section.

  Hereinafter, modes for carrying out the present invention will be described.

  FIG. 1 is a partial explanatory view schematically showing a logical area portion of an example of a CMOS integrated circuit according to the present invention in a plan view.

  The CMOS integrated circuit of this example is based on the premise that a plurality of row region portions 2 are arranged vertically and horizontally, a plurality of wiring layers are provided, and interlayer wirings are connected via vias. Although not shown on the left and right of FIG. 1, different row region portions are arranged.

  In the row region 2 in the horizontal direction, the power supply pattern A10 and the ground pattern A20 are formed in the vertical direction with a thick wiring layer. In general, the uppermost layer is formed of a thick wiring layer.

  In the region where the power supply pattern A10 is formed in the vertical direction, the power supply pattern 11 in the row region 2 is separated into the left and right within the formation region of the vertical power supply pattern A10, and the vertical power supply pattern A10 and the via 30 are interposed. Are connected to each other. Further, a vertical ground pattern B201 is formed in the same layer as the ground pattern 21 of the row region 2 between the power supply patterns 11 of the separated row region 2 and is formed on the ground pattern 21 of the row region 2. Connected directly.

In the region where the ground pattern A20 is formed in the vertical direction, the ground pattern 21 in the row region 2 is separated into left and right within the region where the vertical ground pattern A20 is formed, and the vertical ground pattern A20 and the via 30 are interposed. Are connected to each other. Further, a vertical power pattern B101 is formed in the same layer as the power pattern 11 in the row region 2 between the separated ground patterns 21 in the row region 2, and the power pattern 11 in the row region 2 is formed on the power pattern 11 in the row region 2. Connected directly.

  In the example of FIG. 1, another row region portion is directly connected to the row region portion provided with the power supply wiring and ground wiring on the left and right, and this is repeated to constitute the whole. In this case, the power supply or ground wiring is alternately formed in the uppermost layer pattern between the row regions.

  FIG. 2 is a partial explanatory view schematically showing a row region portion of another example of the CMOS integrated circuit of the present invention in a plan view. In this example, both the ground wiring and the power supply wiring are provided on the left and right sides of the row region portion of FIG. The other row region portions are connected to the left and right of the row region portion in FIG. 2, and this is repeated to constitute the whole. In this case, the uppermost layer pattern in the row region is formed by adjoining both power and ground wirings.

  In the conventional multilayer wiring, the wiring direction of each layer is sequentially limited to only the horizontal direction and only the vertical direction, but in the present invention, it is formed with the lowest power supply, ground wiring layer, and a thick film. The uppermost power supply and ground wiring layers are formed in the same vertical direction. As described above, between the power supply wiring A (or ground wiring A) formed of a thick film in the vertical direction and the lowest ground wiring B (or power supply wiring B), between the separated vias, Layer wiring can be placed. Therefore, the degree of freedom of wiring can be improved and the wiring efficiency can be increased, thereby realizing a higher circuit speed than in the prior art.

  FIG. 3 shows this example, and is a partial explanatory view schematically showing a wiring portion of the row region portion according to the present invention in a plan view. The figure shows an example in which two middle wiring layers 32 and 33 are connected by a via 31 that connects the wiring layers. In this way, wiring between the row regions can be performed.

  In addition, since power and ground can be supplied by two layers of wiring consisting of the lowest layer and a thick film, the width of these wires can be reduced, or the main power and ground wiring can be reduced. The chip size can be reduced. Alternatively, the number of elements in the row region can be increased by reducing the wiring width and using an empty region.

  In addition, even if a voltage drop (IR-Drop) exceeding the allowable range occurs in the power supply or grounding of the row region after arranging and wiring the cell, it can be redesigned while suppressing an increase in chip size compared to the conventional case. it can.

  In the present invention, in the region where the power supply pattern A10 is formed in the vertical direction, the power supply pattern 11 of the row region 2 is separated into the left and right within the formation region of the power supply pattern A10 in the vertical direction, and the contact 35 is included. The via 30 is connected to the power supply pattern A10. For this reason, the resistance value of this wiring may be increased. FIG. 4 is an explanatory view showing a connection portion of the power supply pattern according to the present invention. FIG. 4 (a) shows a conventional connection state, and an example of the present invention is shown in FIG. 4 (b). In this example, a plurality of vias are provided in a row in the wiring direction to cope with this. In the example of FIG. 4A, most of the vias contributing to conduction are provided at the left and right ends, and this is based on this in the example of FIG. 4B. FIG. 4C is another example of the present invention, and two rows are further provided in the wiring direction. If more current is required, it can be handled by increasing the number of vias in this way. The same can be applied to the region where the ground pattern A20 is formed in the vertical direction.

The CMOS integrated circuit of the present invention is designed by arranging and wiring pattern data of basic cells so that the power supply and ground patterns as described above can be formed, and a photomask is produced from this data in the same manner as before, This can be used to produce a wafer process.

DESCRIPTION OF SYMBOLS 1 ... CMOS integrated circuit 2 ... Row area | region part 200 ... Logic area | region part 4 ... Basic cell 8 ... Memory block 9 ... Large-scale logic block 10 ... Power supply pattern, Power supply pattern A
11... Power pattern 101 in the row region portion... Power pattern B
20: Ground pattern, ground pattern A
21... Ground area pattern 201 in the row region... Ground pattern B
30 ... Via 31 ... Via 32 ... Middle wiring layer 33 ... Other middle wiring layers

Claims (3)

In a CMOS integrated circuit in which a plurality of row regions are arranged vertically and horizontally, a plurality of wiring layers are provided, and interlayer wirings are connected via vias,
The power supply pattern A and the ground pattern A are formed in the vertical direction in the uppermost wiring layer having a large film thickness in the row region in the horizontal direction,
In the region where the power supply pattern A is formed in the vertical direction, the power supply pattern in the row region is separated into left and right within the formation region of the vertical power supply pattern A and is connected to the vertical power supply pattern A via each via. The vertical ground pattern B is formed in the same layer as the ground pattern of the row region portion and is directly connected to the ground pattern of the row region portion between the separated power patterns of the row region portion,
In the region where the ground pattern A is formed in the vertical direction, the ground pattern in the row region is separated into left and right within the region where the vertical ground pattern A is formed, and is connected to the vertical ground pattern A via each via. The vertical power supply pattern B is formed in the same layer as the power supply pattern of the row region portion and is directly connected to the power supply pattern of the row region portion between the ground patterns of the separated row region portion. A featured CMOS integrated circuit.   2. The CMOS integrated circuit according to claim 1, wherein a wiring pattern of another layer is formed between regions where the left and right power supply patterns or ground patterns are formed.   A photomask used for forming a wiring layer of the CMOS integrated circuit according to claim 1.

Images