JP2006165040A - Semiconductor device and method of designing pattern thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the process controllability by making the pattern occupancy in the entire semiconductor chip constant. <P>SOLUTION: In a first region 11 in a conductor chip 10 which contributes to logic operation, the first dummy pattern of a fixed size is formed. The first dummy pattern is formed away by 0.5 μm or above from signal interconnections adjacent to the pattern in the horizontal and vertical directions. In order to make the pattern occupancy in the entire semiconductor chip 10 constant among the same products and among the same interconnection layers of the same product, a second dummy pattern is formed in a second region 12 in the semiconductor chip 10 which does not contribute to logical operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a pattern design method for the semiconductor device, and more particularly to arrangement of dummy patterns.

With the miniaturization of semiconductor devices, process control has become difficult. For example, when a damascene wiring is formed by embedding a conductive film 64 in a groove 63 in an insulating film 62 on a substrate 61 as shown in FIGS. 11A and 11B, the damascene wiring is densely arranged as shown in FIG. In the case of a thick wiring, there is a problem that dishing 65 occurs due to CMP (chemical mechanical polishing). Further, as shown in FIG. 13, when the substrate 71 is etched using the resist pattern 72 as a mask to form the element isolation groove 73, there is a problem that a shape abnormality such as a sub-trench occurs. In order to solve these problems, it is effective in process control to arrange a dummy pattern around the circuit pattern.
Specifically, the layout area is divided into a plurality of areas, the pattern occupancy is calculated for each of the divided areas (hereinafter referred to as “divided areas”), and the dummy patterns are arranged so as to be within a predetermined range. A technique has been proposed (see, for example, Patent Document 1).
The arrangement of the dummy pattern is often automatically processed by CAD (computer aided design) at the time of mask creation. Instead of arranging one type of dummy pattern, a method has been proposed in which two or more types of dummy patterns having different sizes are arranged (see, for example, Patent Document 2).

JP 2003-347406 A JP 2001-156072 A

  However, when a wide variety of products such as SoC (system on chip), ASIC (application specific integrated circuit), and microcomputers are developed, the pattern occupancy rate (mesh occupancy rate described later) of the divided area is kept constant for each product. It was difficult. In addition, the pattern occupancy ratio (chip occupancy ratio described later) of the entire chip is not kept constant for each wiring layer of the same product or for each product. For this reason, it takes a long time to obtain process conditions for different wiring layers of the same product or for different products, and there is a problem that process controllability is low.

  SUMMARY An advantage of some aspects of the invention is that it provides a semiconductor device excellent in process controllability and a pattern design method for the semiconductor device.

A semiconductor device according to the present invention includes a fixed-size first dummy pattern formed in a first region that contributes to a logical operation in a semiconductor chip,
And a second dummy pattern formed in a second region that does not contribute to a logical operation in the semiconductor chip so that a pattern occupancy ratio of the entire semiconductor chip becomes a constant value. .

A pattern design method for a semiconductor device according to the present invention is a pattern design method for a semiconductor device having a first region contributing to a logical operation and a second region not contributing to a logical operation in a semiconductor chip,
Disposing a first dummy pattern of a fixed size in the first region at a certain distance or more away from the logic operation circuit pattern;
And a step of arranging a second dummy pattern in the second region so that a pattern occupancy ratio of the entire semiconductor chip becomes a constant value after the first dummy pattern is arranged. is there.

  As described above, according to the present invention, process controllability can be improved by making the pattern occupancy ratio of the entire semiconductor chip constant.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

  As described in the background art, the dummy patterns are arranged so that the pattern occupancy rate (hereinafter referred to as “mesh occupancy rate”) in the area unit of the semiconductor chip is within a specified range. The present invention is characterized in that, in order to stably manufacture a deep submicron semiconductor device, the pattern occupancy ratio (hereinafter referred to as “chip occupancy ratio”) of the entire semiconductor chip is within a specified range together with the mesh occupancy ratio. Have. That is, in the present invention, two pattern occupancy rates are controlled in the layout design stage and the mask creation stage.

Embodiment 1 FIG.
FIG. 1 is a plan view for explaining a semiconductor device according to the first embodiment of the present invention. Specifically, FIG. 1 is a schematic plan view showing the layout of the entire semiconductor chip.

As shown in FIG. 1, the semiconductor chip 10 has a first region 11 that contributes to a logical operation and a second region 12 that does not contribute to a logical operation. The semiconductor chip 10 has a size of several mm square, for example.
In the present invention, the pattern occupation ratio in the entire semiconductor chip 10 is constant regardless of the type of product (such as SoC and ASIC). Furthermore, the pattern occupancy rate of the entire semiconductor chip 10 is constant regardless of the wiring layer.

  The first region 11 is, for example, a logic core region or a memory cell region, and is a region where a semiconductor element such as a transistor is formed by fine processing, and a signal wiring is formed thereabove. The first area 11 is an area where the circuit performance is easily affected by the dummy pattern. Specifically, the region is easily affected by the stray parasitic capacitance due to the dummy pattern.

  The second area 12 is, for example, an empty area 12a where no pattern is formed, an I / O area 12b around the semiconductor chip, and a power supply and ground wiring formation area 12c. Unlike the first region 11, the second region 12 is a region in which the circuit performance is not easily affected by the dummy pattern. As the vacant area 12a constituting the second area 12, it is possible to set an area that is 5 μm or more, more preferably 10 μm or more away from an adjacent signal wiring and that is not formed with a functional pattern.

  FIG. 2 is a schematic plan view showing the arrangement of dummy patterns in the first region shown in FIG. FIG. 3 is a schematic plan view showing the arrangement of dummy patterns in the second region shown in FIG.

  As shown in FIG. 2, in the first region 11, the first dummy pattern 23 is arranged with emphasis on circuit performance. That is, in the first region 11, the dummy pattern 23 is disposed so as not to add a floating parasitic capacitance to the signal wirings 21 and 22. A dummy pattern 23 is arranged so as not to add floating parasitic capacitance to the wiring 21 adjacent in the horizontal direction and the wiring 22 adjacent in the vertical direction. The dummy pattern 23 and the wirings 21 and 22 are preferably separated by 0.5 μm or more. The distance D1 between the dummy pattern 23 and the wiring 21 adjacent in the vertical direction (lower layer or upper layer) and the distance D2 between the dummy pattern 23 and the wiring 22 adjacent in the horizontal direction (same layer) can be set to 1 μm, for example. is there. Therefore, the dummy pattern 23 is not arranged at the position indicated by the dotted line in FIG. The line width W1 of the wiring 21 and the line width W2 of the wiring 22 are, for example, 0.2 μm.

The dummy pattern 23 has a fixed size. That is, the dummy pattern arranged in the first region of the first wiring layer constituting the semiconductor device and the dummy pattern arranged in the first region of the second wiring layer have the same size. Furthermore, it is assumed that the sizes of the dummy patterns arranged in the first region in different products (such as SoC and ASIC) are the same.
The width W3 and the pitch P1 of the dummy pattern 23 can be set to 1 μm, for example.
The mesh occupancy is controlled by the dummy pattern 23 arranged in the first region 11, and the controllability of a microfabrication process such as dry etching or CMP can be improved. It is assumed that the dummy pattern 23 in the first region 11 is only the circuit verified by the TEG mask.

In addition, the shape of the dummy pattern 23 arranged in the first region 11 can be a line shape instead of a pad shape (the same applies to a dummy pattern 25 described later).
Also, instead of one type of dummy pattern 23, two types of dummy patterns having different sizes can be arranged. Also in this case, two types of fixed-size dummy patterns are arranged.
Further, when the first region 11 is configured by a plurality of circuit blocks, for example, in the case of a mixed circuit of a logic circuit and a memory, the size of the dummy pattern may be different for each circuit block.

The control of the pattern occupancy by the dummy pattern arrangement and the increase of the parasitic capacitance by the dummy pattern arrangement have a trade-off relationship. FIG. 4 is a conceptual diagram showing the relationship between the dummy pattern and the parasitic capacitance. Specifically, FIG. 4A is a diagram showing an ideal state viewed from the design, FIG. 4B is a diagram showing a first dummy pattern arrangement example, and FIG. It is a figure which shows the example of dummy pattern arrangement | positioning.
As shown in FIG. 4A, in the performance verification stage (TEG mask), no dummy wiring is arranged between the first wiring 35 and the third wiring 37, and the first wiring 35 is parasitic. The capacity is small.
As shown in FIG. 4B, a dummy active region 33 of the substrate 31 separated by the element isolation 32 is formed, and a narrow dummy second wiring 36a is formed between the first wiring 35 and the third wiring 37. Is formed, the parasitic capacitance with respect to the first wiring 35 is increased.
As shown in FIG. 4C, when a dummy gate electrode 34 is formed on the dummy active region 33 and a thick dummy second wiring 36b is formed between the first wiring 35 and the third wiring, The parasitic capacitance for one wiring 35 is further increased.

FIG. 5 is a conceptual diagram showing a dummy pattern placement prohibition region in the first embodiment. As shown in FIG. 5, for the signal wiring 35 that is critical in terms of circuit, it is preferable that a range that is separated by a predetermined distance of 0.5 μm or more in the horizontal direction and the vertical direction is the prohibited region 40. is there. The reason for this will be described below.
FIG. 6 is a conceptual diagram showing dummy wirings arranged in the same layer as the signal wirings and in the upper and lower layers thereof.
As shown in FIG. 6, dummy wirings 39 are arranged in the same layer as the signal wirings 38, that is, in the horizontal direction. The distance between the horizontal signal wiring 38 and the dummy wiring 39 is, for example, 1 μm. The horizontal dummy wiring 39 does not increase the parasitic capacitance of the signal wiring 38. The line width of the signal wiring 38 is, for example, 0.18 μm. In addition, dummy wirings (also referred to as “floating dummy metal”) 39 are also arranged in the upper and lower layers of the signal wiring 38, that is, in the vertical direction and the oblique direction. The signal wiring 38 and the dummy wiring 39 are insulated by an interlayer insulating film (not shown). As the interlayer insulating film, a low-k film having a relative dielectric constant (for example, k = 3 to 3.5) lower than that of the silicon oxide film can be used. The signal wiring 38 and the dummy wiring 39 are Cu wiring.
FIG. 7 is a diagram showing the relationship between the distance between the signal wiring and the upper and lower layer dummy wirings shown in FIG. 6 and the parasitic capacitance ratio. Specifically, the influence of the dummy wirings 39 arranged on the upper and lower layers of the signal wiring 38 on the parasitic capacitance of the signal wiring 38 is shown. The parasitic capacitance ratio on the vertical axis in FIG. 7 is the ratio of the parasitic capacitance of the signal wiring when the dummy wiring is arranged in the upper and lower layers to the parasitic capacitance of the signal wiring when the dummy wiring is not arranged in the upper and lower layers of the signal wiring. . Specifically, when the parasitic capacitance ratio is 1.05, the parasitic capacitance of the signal wiring 38 is increased by 5% by arranging the dummy wirings 39 in the upper and lower layers of the signal wiring 38. Patterns 1 to 3 are dummy wirings arranged in upper and lower layers, respectively, and have different pattern occupancy rates. The pattern occupancy is determined by the pitch and size of the dummy wiring. For example, the occupation ratios of the patterns 1, 2, and 3 are 30, 20, and 10%, respectively. As shown in FIG. 7, the higher the pattern occupancy of the dummy wirings 39 arranged in the upper and lower layers, the larger the parasitic capacitance of the signal wirings 38. Here, from the viewpoint of circuit operation, it is preferable to suppress the increase in parasitic capacitance of the signal wiring 38 to 5% or less, that is, to suppress the parasitic capacitance ratio to 1.05 or less. Accordingly, as described above, the distance between the signal wiring 38 and the upper and lower layer dummy wirings 39 is preferably 0.5 μm or more. As a result, it is possible to prevent the parasitic capacitance from being added due to the dummy pattern which is not present at the design stage (TEG mask) and is added at the time of creating the mask.
In general, the dummy pattern is often arranged starting from a certain place (for example, the first wiring 35 or the signal wiring 38). However, it is desirable that the positional relationship between the dummy patterns arranged in the circuit is exactly the same as that of the TEG mask whose performance has been verified. For this reason, it is preferable to set a plurality of dummy pattern generation rule starting points and arrangement prohibition ranges.

  FIG. 8 is a cross-sectional view for explaining a semiconductor device to which a dummy pattern arrangement prohibited region is applied. FIG. 9 is a cross-sectional view for explaining a semiconductor device to which the dummy pattern arrangement prohibited region is not applied. 8 and 9 show the first region, and a MOSFET is formed in the first region.

  As shown in FIGS. 8 and 9, a gate electrode 44 is formed in the active region of the substrate 41 separated by the element isolation 42 via a gate insulating film 43, and a sidewall 46 is formed on the side wall of the gate electrode 44. Is formed. An extension region 45 and a source / drain region 47 are formed so as to sandwich a channel region below the gate electrode 44. A plug 49 connected to the source / drain region 47 is formed in the interlayer insulating film 48 covering the MOSFET. The plug 49 is electrically connected to the wiring 51 and the multilayer wiring on the upper layer.

Here, the arrangement of the dummy wiring pattern around the isolated signal wiring 57 constituting the multilayer wiring will be described.
As shown in FIG. 8, in the case where the placement prohibited area is applied, only the dummy wiring patterns 54 and 60 are arranged obliquely above and below the isolated signal wiring 57, and above and below the isolated signal wiring 57. No dummy wiring pattern is arranged. Therefore, no extra parasitic capacitance is added to the isolated signal wiring 57. In recent years, since the device dimensions in the vertical direction (stacking direction) have been scaled in addition to the horizontal direction, the influence of the stray parasitic capacitance of the dummy pattern on the design circuit cannot be ignored. The influence of parasitic capacitance can be prevented.
On the other hand, as shown in FIG. 9, dummy wiring patterns 54 and 60 are also arranged above and below the isolated signal wiring 57 when the above-described prohibited area is not applied. In this case, an extra parasitic capacitance is added to the isolated signal wiring 57.

As shown in FIG. 3, in the second region 12, dummy patterns 25 are arranged around the wiring 24 so that the chip occupation ratio is constant for each product or wiring layer. In other words, the chip occupancy is optimized by the arrangement of the dummy patterns 25. Since the second region 12 has little influence on the circuit performance, the size and arrangement method of the dummy pattern 25 can be made different from those of the dummy pattern 23 in the first region 11. In consideration of pattern design and inspection time, it is preferable to increase the size of the dummy pattern 25. The distance between the dummy pattern 25 and the adjacent wiring 24 may be shorter than the distances D1 and D2 of the first region 11.
The chip occupation rate is controlled by the dummy pattern 25 arranged in the second region 12. As a result, the time required for obtaining process conditions for each different wiring layer of the same product or for each different product can be greatly reduced, and the process controllability can be improved.

  As described above, in the first embodiment, process controllability can be improved by arranging dummy patterns in consideration of not only the mesh occupancy but also the chip occupancy. As well as improving the controllability of fine processing processes such as dry etching and CMP by controlling the mesh occupancy as in the past, control of the chip occupancy without adjusting the process conditions for each product and wiring layer A stable semiconductor device can be manufactured. In addition, since the circuit characteristics can be stabilized, it is possible to cope with a critical path.

  The present invention can be applied not only to the formation of the metal wiring described above, but also to other processes in which process control is difficult. For example, the present invention can also be applied to an active region forming process for forming dummy element isolation around the element isolation, a gate electrode forming process, and an ion implantation mask forming process.

Embodiment 2. FIG.
FIG. 10 is a flowchart for explaining a pattern design method for a semiconductor device according to the second embodiment of the present invention.
First, the first area 11 and the second area 12 shown in FIG. 1 are recognized (step S11). Note that the chip occupation ratio is set in advance. The chip occupation ratio can be set within a range of 15 to 25%, for example.

Next, a dummy pattern is arranged in the region where the circuit pattern of the first region 11 is not formed in consideration of the parasitic capacitance (step S12). At this time, the mesh occupation ratio of the first region 11 is controlled. The size of the dummy pattern arranged in the first area is fixed.
Then, the pattern occupation ratio of the first region is calculated (step S13).

Next, in consideration of the pattern occupation ratio of the first area calculated in step S13, dummy patterns are arranged in the second area so that the chip occupation ratio becomes a set value (step S14).
After the dummy pattern is arranged in the second area, the chip occupation rate is calculated (step S15).

Next, it is determined whether or not the chip occupation rate calculated in step S15 is equal to the set value (step S16). If it is determined that they are equal, the arrangement of the dummy patterns in the first and second regions is determined, and a mask is created (step S18).
On the other hand, if it is determined that they are not equal, the dummy pattern is rearranged in the second area (step S17). Here, if the calculated value is smaller than the set value, the density of the dummy patterns in the second region may be increased. If the calculated value is larger than the set value, the density of the dummy pattern in the second region may be lowered. After the rearrangement, step S16 is performed again.

For example, if the ratio of the first area to the second area is about 8: 2, and the pattern occupancy ratio of the first area is 20%, the chip occupancy ratio is 25% due to the dummy pattern arrangement in the second area. If you want to.
When the pattern occupancy ratio of the first area is high, the chip occupancy ratio can be made lower than the pattern occupancy ratio of the first area by arranging the dummy patterns sparsely in the second area.

As described above, in the second embodiment, the dummy pattern is arranged in the first region 11 in consideration of the parasitic capacitance, and then the pattern occupation ratio (chip occupation ratio) of the entire semiconductor chip is made constant. 2 A dummy pattern is arranged in the region 12. Thereby, the effect similar to Embodiment 1 can be acquired.
Further, since the chip occupancy is calculated after the dummy pattern is arranged in the second region and compared with the set value, the chip occupancy can be controlled with high accuracy.

It is a top view for demonstrating the semiconductor device by Embodiment 1 of this invention. FIG. 2 is a schematic plan view showing the arrangement of dummy patterns in a first area shown in FIG. 1. It is a schematic plan view which shows arrangement | positioning of the dummy pattern in the 2nd area | region shown in FIG. It is a conceptual diagram which shows the relationship between a dummy pattern and parasitic capacitance. In Embodiment 1 of this invention, it is a conceptual diagram which shows the arrangement | positioning prohibition area | region of a dummy pattern. It is a conceptual diagram which shows the dummy wiring arrange | positioned in the same layer as a signal wiring and the upper and lower layers. It is a figure which shows the relationship between the distance of a signal wiring and upper and lower layer dummy wiring, and a parasitic capacitance ratio. It is sectional drawing for demonstrating the semiconductor device to which the arrangement | positioning prohibition area | region of a dummy pattern is applied. It is sectional drawing for demonstrating the semiconductor device which is not applying the arrangement | positioning prohibition area | region of a dummy pattern. It is a flowchart for demonstrating the pattern design method of the semiconductor device by Embodiment 2 of this invention. It is sectional drawing which shows the formation process of damascene wiring. It is sectional drawing which shows the dishing produced at the time of CMP. It is sectional drawing which shows the subtrench produced at the time of formation of the groove | channel for element isolation.

Explanation of symbols

  10 semiconductor chip, 11 first area, 12 second area, 12a free area, 12b I / O area, 12c power and ground wiring area, 21, 22 signal wiring, 23 dummy pattern, 24 wiring, 25 dummy pattern, 31 substrate 32 element isolation, 33 dummy active region, 34 dummy gate electrode, 35 first wiring, 36a, 36b dummy second wiring, 37 third wiring, 38 signal wiring, 39 dummy wiring, 40 forbidden area, 41 substrate, 42 element Separation, 43 gate insulating film, 44 gate electrode, 45 extension region, 46 sidewall, 47 source / drain region, 48, 50, 52, 53, 55, 56, 58, 59 interlayer insulating film, 49 plug, 51 wiring, 54, 60 Dummy wiring pattern 57 isolated signal wiring.

Claims (7)

A fixed-size first dummy pattern formed in a first region that contributes to a logical operation in the semiconductor chip;
A semiconductor device comprising: a second dummy pattern formed in a second region that does not contribute to a logical operation in the semiconductor chip so that a pattern occupancy ratio in the entire semiconductor chip becomes a constant value. The semiconductor device according to claim 1,
The second area includes an empty area where a pattern in the semiconductor chip is not disposed, a pad area disposed on the outer periphery of the semiconductor chip, and an area where a power supply and a ground wiring are formed. Semiconductor device. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the first dummy pattern is a dummy wiring pattern that does not add a floating parasitic capacitance to the signal wiring arranged in the first region. The semiconductor device according to claim 3.
The semiconductor device according to claim 1, wherein the first dummy pattern is disposed at a distance of 0.5 μm or more from the signal wiring adjacent in the horizontal direction and the vertical direction. A pattern design method for a semiconductor device having a first region contributing to a logical operation and a second region not contributing to a logical operation in a semiconductor chip,
Disposing a first dummy pattern of a fixed size in the first region at a certain distance or more away from the logic operation circuit pattern;
A step of arranging a second dummy pattern in the second region so that a pattern occupancy ratio of the entire semiconductor chip becomes a constant value after the first dummy pattern is arranged. Pattern design method. In the semiconductor device pattern design method according to claim 5,
The second area includes an empty area where a pattern in the semiconductor chip is not disposed, a pad area disposed on the outer periphery of the semiconductor chip, and an area where a power supply and a ground wiring are formed. Semiconductor device pattern design method. In the pattern design method of the semiconductor device according to claim 5 or 6,
The method of designing a pattern of a semiconductor device, wherein the first dummy pattern is arranged at a distance of 0.5 μm or more from a signal wiring in a horizontal direction and a vertical direction.

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