JPS61158162A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To effectively suppress the voltage variation to generate in the power wirings by a method wherein the metal wiring layer on the power source side and the metal wiring layer on the grounding side having the same potential as that of the semiconductor substrate are respectively laminated on the semiconductor substrate as the lower layer and the upper layer and dielectrics are made to interpose between these metal wiring layers and between the metal wiring layer on the side of the lower layer and the semiconductor substrate. CONSTITUTION:In case a master slice system called gate array is applied to this LSI, supply voltage VDD is impressed on a metal wiring 21, which is wired in the lower layer (first layer) of the power wiring main line part of the LSI, through a pad PD1 when the semiconductor substrate 10 of the LSI is assumed to have an earth potential and a metal wiring 22, which is wired in the upper layer (second layer) of the LSI, is earthed through a pad PD2. Out of metal wirings 23 and 24, which are respectively a power wiring in a gate array part 30, the metal wiring 23 to be selected in a VDD potential are connected with the metal wiring 21, which is the first-layer wiring in the same manner as the metal wirings 23, in a T-shaped configuration and the metal wirings 24 to be selected in a GND potential are stereophonically connected with the metal wiring 22, which is the second-layer wiring in the same manner as the metal wirings 24, through contact holes.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit K>
This invention relates to improvements in the power supply line wiring structure.

[Technical Background of the Invention and Problems Therewith] Generally, a semiconductor integrated circuit includes a large number of semiconductor active elements and two types of power supply wiring, one on the power supply side and one on the ground side, for supplying power to these semiconductor active elements.

By the way, in such semiconductor integrated circuits, not only is noise introduced from the outside into the power supply wiring, but also noise is generated in the power supply wiring due to current pulses caused by rapid internal switching operations, and the noise is This has the disadvantage of adversely affecting circuit operation. In particular, in large-capacity dynamic RAM and highly integrated LSIs, there are many circuit elements that operate simultaneously, so voltage fluctuations are likely to occur in the power distribution circuit due to the operation of these elements.
This also makes the circuit operation unstable.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that can effectively suppress voltage fluctuations caused by noise and other stains in wiring, and can significantly improve power supply capability to internal circuit elements.

[Summary of the invention]

In this invention, of the first and second metal wiring layers arranged as the two types of power wiring on the semiconductor substrate, the metal wiring layer on the side having a different potential from the semiconductor substrate (so-called power supply side) and the metal wiring layer on the side having a different potential from the semiconductor substrate (so-called power supply side) The first and second metal wiring layers Among them, the metal wiring layer on the power supply side is stacked on the bottom layer, and the metal wiring layer on the ground side, which has the same potential as the semiconductor substrate, is stacked on the top layer. A dielectric material is interposed between the metal wiring layer and the semiconductor substrate to form a capacitive element tube. By using such a wiring layer structure, υ
The above-mentioned ground capacitance of the power supply side metal wiring layer includes, in addition to the direct capacitance with the semiconductor substrate, the capacitance with the ground side metal wiring layer connected in parallel with the same constraints. However, the grounding capacity of the power supply will increase dramatically.

Further, it is more preferable from a practical point of view that the laminated structure of the metal wiring layer serving as the power supply wiring is adopted only in the power supply wiring area other than the element area where the active element is arranged, that is, in the power supply wiring trunk part, and is applied to the element area. Power is supplied to each element through third and fourth metal wirings, which are not laminated and are electrically connected to the metal wiring layers having a laminated structure, respectively. In general, in the element area, in addition to the power wiring, there are many wirings to achieve various required logical functions, so it is possible to increase the above-mentioned capacitance to ground only by using the main power wiring line. Returning to the normal one-layer power supply wiring in the element region where the wiring is complicated is effective in facilitating the manufacture of the semiconductor integrated circuit and in preventing the occurrence of local areas where wiring is impossible. This effect is particularly remarkable when the active elements in the element region are unit functions or elements connected in both directions.

〔Effect of the invention〕

- Thus, according to the semiconductor integrated circuit according to the present invention, the capacitance to ground of the power supply side metal wiring layer can be reliably increased. Therefore, even if the power supply voltage fluctuates as described above, this is effectively suppressed, and stable power is always supplied to the circuit elements. This can be said in other words.

This means that the power supply efficiency to circuit elements is improved and the electrical characteristics of the integrated circuit itself are improved. Of course, this is expected to further speed up the operation of the integrated circuit.

Further, according to the present invention, at least the metal wiring layer of the power supply wiring main line portion (which is usually the wiring layer required to have the widest line width among the wirings of the integrated path) is formed by laminating. The space factor also improves. Therefore, this invention greatly contributes to improving the degree of integration.

In particular, a multilayer power supply wiring structure is adopted only in the main line section, and the power supply wiring St-
If the power supply is made larger so that power can be supplied through the integrated circuit, it will be beneficial in terms of ease of manufacturing the integrated circuit.

[Embodiments of the invention]

First, the present invention will be described in detail with reference to FIG.

In FIG. 8≦, a semiconductor substrate where IO is at a ground potential, a metal wiring (power supply side metal wiring) which is at a different potential with a potential difference V from this semiconductor substrate IO among the 20 power supply wirings,
Similarly, 22 indicates this semiconductor substrate 10 among the power supply wiring.
Between metals that are at the same ground potential as (!Ground side metal wiring)
In this invention, as shown in FIG. 8, a metal wiring 21 at a different potential from the semiconductor substrate 10 is used as the first wiring, and a metal wiring 22 at the same potential as the conductor substrate IO is placed on the semiconductor substrate 10. As the second layer wiring, the capacitance 91 and C2t? shown in the same figure, respectively, are used. Formed by stacking and stacking. As a result, conventionally, that is, in a system in which the power supply wiring has a single-layer structure, only the capacitance CI between the power supply side metal wiring 21 and the semiconductor substrate 10 was effective as the grounding capacitance of the power supply. As the grounding capacitance, the capacitance C2 between the same metal wiring 21 and the ground side metal wiring 22, which are connected in parallel with the capacitance JIC1 with equal constraints, is also added. Capacity will inevitably increase.

This is the principle of increasing the ground capacity in this invention,
Fluctuations in the power supply voltage are effectively suppressed by such an increase in the grounding capacity.

FIG. 1 shows an embodiment of a semiconductor integrated circuit according to the present invention constructed based on this principle.

In this embodiment, the present invention is applied to a master switch type LSI called a gate array.

In other words, this LSI basically consists of a P-door array section 30 consisting of many unit functional elements SL arranged in a grid pattern on a semiconductor substrate IO, and accessory circuits 40 and 50 consisting of arithmetic circuits, memory circuits, etc. Only the wiring pattern in the wiring area on the unit functional element SL or between the unit functional elements BL is designed and manufactured according to the type of LSI.

Now, in this embodiment, for such an LSI, the first
As shown in the figure, a laminated structure of power supply wiring based on the above principle is adopted for the so-called power supply wiring trunk section that commonly supplies power to the f-) array section 30 and the attached circuits 40 and 50, and
Power is supplied to each unit functional element SL in the door array section 30 through metal wirings 23 and 24 having a normal single-layer structure. That is, if the semiconductor substrate 10 of this IAI is at ground potential, the power supply voltage (VDD) is applied to the metal wiring 21 in the lower layer (first layer) of the power supply wiring trunk section through the notad PDI. In this way, the metal wiring 22 wired in this upper layer (second layer) is grounded (GND) through the t4-doped PD2, and the metal wiring 22 which is the power wiring in the r-dore array section 30 Of 23 and 24, v′DD
The metal wiring 23 selected for the potential is connected in a T-shape with the metal wiring 21, which is also the first layer wiring, and the metal wiring 24 selected for the GND potential is connected to the metal wiring 22, which is the second layer wiring, through a contact hole. It is three-dimensionally connected through.

This structure will be described in further detail with reference to FIGS. 2-4.

FIG. 2 shows an enlarged view of the circle CC in FIG. 1, and also shows an example of the structure of the unit functional element 8L.

That is, this unit functional element St is composed of a P-well 31, a -diffusion layer 32m+32bt32e, and r-) electrodes 34a and 34b made of polysilicon or the like on a semiconductor substrate 10 which is an n-type substrate. In two n-channel (nch) 2 nnostars and the same substrate IO, P+ diffusion 71133 m, 33
b, 33e, and dart electrode 34a.

34c and two P channels (Pe
h)) It has a total of four transistors, and has a circuit configuration as shown in FIG. 3.

Assuming such a configuration of the unit functional element SL, each cross-sectional structure t- It is shown in Figure 4.

First, FIG. 4(A) shows a cross-sectional structure taken along the line A-A' in FIG. On a certain semiconductor substrate 10, a dielectric layer 61 made of silicon oxide (5tO2), for example, and a metal wiring layer 2 having a vDD potential are formed.
1 and this is also, for example, 810. A second dielectric layer 62 consisting of a metal wiring layer 22 having a GND potential is sequentially deposited.

Note that for these metal wiring layers 21 and 22, aluminum or ram (HT) is used, for example. In the portions of the dielectric layers 61 and 62 that are in contact with the metal wiring layers 21 and 22, the capacitances CI and C2 (see FIG. 8) described in the above principle are formed, respectively.

Next, FIG. 4(B) shows the cross-sectional structure taken along line B-B' in FIG.
As shown in the figure, in the part where the metal wirings that have a potential are connected, the unit functional element SL is wired in advance as the first layer wiring, and is connected to the unit functional element SL through the contact hole CHI provided in the dielectric layer 61. P channel transistor 1
″:)K The electrically coupled metal wiring layer 24 and the metal wiring 22 wired as the second layer wiring are connected to the dielectric layer 6.
They are sterically bonded via a contact hole CH2 provided in 2. The structure of the TIL source wiring trunk section (the left end portion in the figure) is basically the same as that shown in FIG. 4 (CA)K. In the octopus portion, even if the first layer wiring is the same, the metal wiring layer 24 in the element region
and the metal wiring layer 21 in the main line section are electrically insulated. In FIG. 4 (in Peng), reference numeral 63 indicates the dirt insulating film of the transistor described above.
The same applies to the figure (cut).

and FIG. 4 (Q is a tortoise-shaped bridge showing the cross-sectional structure taken along line c-c' in FIG.
As shown in the figure, in the portion where the metal wirings at potential are connected, the unit functional element 8 is connected to the unit functional element 8 through the contact hole CH3 provided in the dielectric layer 61 in the element region.
The metal wiring layer 23 electrically coupled to one of the L n-channel transistors and the metal wiring layer 21 constituting the power supply wiring trunk section are both integrally formed as a first layer wiring, and this metal wiring layer A metal wiring layer 22, which also constitutes the power supply wiring main line portion, is laminated on top of the metal wiring layer 21 as a second layer wiring with a dielectric layer 62 interposed therebetween.

In this way, by making the wiring structure of the power supply wiring a laminated structure based on the above-mentioned principle, the grounding capacity of the power supply increases dramatically, making it stable and highly efficient for the above-mentioned transistors, etc. power supply.

In addition, as in this embodiment, only the power supply wiring trunk section has a laminated structure in order to increase the above-mentioned capacitance to ground, and power is supplied to each element in the element area by the metal wiring layer 2 having the laminated structure.
If this is done through the third and fourth metal wiring layers 23 and 24 of a single layer structure, which are electrically connected to 1 and 22, respectively, wiring between elements in the same element region becomes easy. In particular, these master slice type LSIs
[Odor] is also useful in preventing the occurrence of local unwiring areas.

In this embodiment, the first layer wiring of the main power supply wiring section having a laminated structure, that is, the metal wiring layer 21, is laid on the dielectric layer 61 deposited flatly as shown in FIG. However, in addition, for example, as shown in FIG. 5 as a sectional view corresponding to the part corresponding to FIG. , a groove M is previously formed along the portion of the dielectric layer 61 where the metal wiring layer 21 is laid, and the metal wiring layer 21 is deposited over the formed groove M. In this way, if the layer thickness of the portion of the dielectric layer 61 where the metal wiring layer 21 is laid down is actively reduced, the capacitance to ground of the metal wiring layer 21 increases accordingly. . In other words, great effects can be expected from the above-mentioned effects of this invention. Figures 4(B) and (
Although the illustration of the portion corresponding to C') is omitted, the structure of the main power supply wiring section is based on that shown in FIG. 5.

However, the groove M may be formed in another manner as shown in FIG. 6.

By the way, the above-mentioned principle of this invention also means the following.

An example in which the same principle is applied to a cMOS circuit will be described with reference to FIG. .

That is, at 0M08, the n-type substrate 11 is at VDD.
Since the potential KA and the P well 12 are at the VSS potential, when forming a power supply wiring on the n-type substrate 11, the seventh
As shown on the right side of the figure, a metal wiring layer 71 at a VaS potential different from that of the substrate 11 is formed in the lower layer as a first layer wiring, and a metal wiring layer 72 at a VDD potential is formed in the upper layer as a second layer wiring. Conversely, when forming a power supply wiring on the P-well 12, as shown on the left side of FIG. The metal wiring layer 71 at the vSS potential is formed as the second layer wiring in the lower layer, and the metal wiring layer 71 at the vSS potential is formed in the upper layer as the second layer wiring.Even if the stacked layer 1A of the two metal wiring layers is reversed, If the same principle is actively fulfilled according to the potential of the semiconductor substrate (the P-well is also a substrate with a specific characteristic, in this case the P-well 12 is also regarded as an independent semiconductor substrate), which becomes the base. , the same effect as described above can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing one embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a partially enlarged plan view of the embodiment shown in FIG. 1, and FIG. 3 is a unit function shown in FIG. 2. An equivalent circuit diagram showing the electrical configuration of the element, Figure 4 is A-A' in Figure 2.
5 and 6 are cross-sectional views schematically showing the cross-sectional structure of the same embodiment at the line section, the line section B-B', and the section line C-C'.
7 and 7 are respectively cross-sectional views schematically showing partial cross-sectional structures of other embodiments of the semiconductor integrated circuit according to the present invention, and FIG. 7 is a schematic diagram showing the principle of the present invention. 10.11...Semiconductor substrate, 21, 22.23°24
．． 71, 72...Metal wiring layer, 61.62...Dielectric layer-"SL...Unit functional element.

Claims (3)

[Claims] (1) Two metal wiring layers, a first and a second metal wiring layer, which are arranged as power wiring lines, are laminated and formed on a semiconductor substrate having a large number of semiconductor active elements, and these first and second metal wiring layers are formed. between the layer and the semiconductor substrate, and the first
A semiconductor integrated circuit in which a dielectric material is interposed between a metal wiring layer and a second metal wiring layer to form a capacitance element, the first metal wiring layer and the second metal wiring layer comprising: A semiconductor integrated circuit in which a metal wiring layer having the same potential as the semiconductor substrate is laminated as an upper layer, and a metal wiring layer having a different potential from the semiconductor substrate as a lower layer. (2) The semiconductor integrated circuit according to claim 1, wherein the first and second metal wiring layers are main power supply wirings arranged in a power supply wiring area other than the element area. (3) Claim (2), wherein the semiconductor active device is a unit functional device connected by a master slice method.
Semiconductor integrated circuit described in Section 1.