JPS639137U - - Google Patents
Info
- Publication number
- JPS639137U JPS639137U JP10298986U JP10298986U JPS639137U JP S639137 U JPS639137 U JP S639137U JP 10298986 U JP10298986 U JP 10298986U JP 10298986 U JP10298986 U JP 10298986U JP S639137 U JPS639137 U JP S639137U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- power supplies
- insulating film
- interposed therebetween
- same position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案のチツプ周縁における実施例の
平面図、第２図は従来例の平面図である。
１……高電位電源ＶＤＤの主幹配線、２……Ｇ
ＮＤの主幹配線、３……ボンデイングパツド、４
……入出力回路、５……内部回路、６……チツプ
端縁、７，８……分枝配線。
FIG. 1 is a plan view of an embodiment of the chip periphery of the present invention, and FIG. 2 is a plan view of a conventional example. 1...Main wiring of high potential power supply VDD, 2...G
ND main wiring, 3...Bonding pad, 4
...Input/output circuit, 5...Internal circuit, 6...Chip edge, 7, 8...Branch wiring.
Claims (1)
回路において、少なくとも、前記電源のうち２電
源の主幹となる配線を絶縁膜を介して同じ位置に
上下２層の構造としたことを特徴とする半導体集
積回路。 A semiconductor integrated circuit having a multilayer wiring structure having a plurality of power supplies, characterized in that at least the main wiring for two of the power supplies is arranged in upper and lower layers at the same position with an insulating film interposed therebetween. integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10298986U JPS639137U (en) | 1986-07-03 | 1986-07-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10298986U JPS639137U (en) | 1986-07-03 | 1986-07-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639137U true JPS639137U (en) | 1988-01-21 |
Family
ID=30975136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10298986U Pending JPS639137U (en) | 1986-07-03 | 1986-07-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639137U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60206161A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Semiconductor integrated circuit |
| JPS6164142A (en) * | 1984-09-06 | 1986-04-02 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS61158162A (en) * | 1984-12-28 | 1986-07-17 | Toshiba Corp | Semiconductor integrated circuit |
-
1986
- 1986-07-03 JP JP10298986U patent/JPS639137U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60206161A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Semiconductor integrated circuit |
| JPS6164142A (en) * | 1984-09-06 | 1986-04-02 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS61158162A (en) * | 1984-12-28 | 1986-07-17 | Toshiba Corp | Semiconductor integrated circuit |