JPS61106048U - - Google Patents
Info
- Publication number
- JPS61106048U JPS61106048U JP19152584U JP19152584U JPS61106048U JP S61106048 U JPS61106048 U JP S61106048U JP 19152584 U JP19152584 U JP 19152584U JP 19152584 U JP19152584 U JP 19152584U JP S61106048 U JPS61106048 U JP S61106048U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- capacitive load
- circuit device
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 2
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案による半導体集積回路装置の模
式図、第２図は本考案による半導体集積回路装置
の一例の要部の拡大平面図、第３図は他の例の模
式図、第４図は従来の半導体集積回路装置の出力
回路の模式図である。
Ｓ……出力トランジスタ、１……その電源線、
２……電源部、Ｃ，Ｃ１，Ｃ２，Ｃ３……外部容
量性負荷、ｌ……誘導成分、Ｌ，Ｌ１，Ｌ２，Ｌ
３……誘導性負荷。
FIG. 1 is a schematic diagram of a semiconductor integrated circuit device according to the present invention, FIG. 2 is an enlarged plan view of essential parts of an example of a semiconductor integrated circuit device according to the present invention, FIG. 3 is a schematic diagram of another example, and FIG. 4 1 is a schematic diagram of an output circuit of a conventional semiconductor integrated circuit device. S... Output transistor, 1... Its power line,
2...Power supply section, C, C1 , C2 , C3 ...External capacitive load, l...Inductive component, L, L1 , L2 , L
3 ...Inductive load.
Claims (1)
導体集積回路装置において、その半導体基体上に
設けられた出力配線パターン自体に、この出力配
線パターンに対する上記外部容量性負荷との接続
リードのボンデイングパツド部の近傍で１巻回以
上繞るパターン部を形成し、主としてこのパター
ン部によつて上記出力回路の電源線と上記外部容
量性負荷との間に誘導性負荷が形成されるように
した半導体集積回路装置。 In a semiconductor integrated circuit device having an output circuit for driving an external capacitive load, an output wiring pattern provided on the semiconductor substrate itself has a bonding pad portion of a connection lead for connecting the external capacitive load to the output wiring pattern. A semiconductor integrated circuit comprising: a pattern portion that extends one turn or more in the vicinity of the semiconductor integrated circuit; circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19152584U JPS61106048U (en) | 1984-12-18 | 1984-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19152584U JPS61106048U (en) | 1984-12-18 | 1984-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61106048U true JPS61106048U (en) | 1986-07-05 |
Family
ID=30748963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19152584U Pending JPS61106048U (en) | 1984-12-18 | 1984-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61106048U (en) |
-
1984
- 1984-12-18 JP JP19152584U patent/JPS61106048U/ja active Pending