JPH0256461U

JPH0256461U -

Info

Publication number: JPH0256461U
Application number: JP13425988U
Authority: JP
Priority date: 1988-10-14
Filing date: 1988-10-14
Publication date: 1990-04-24
Anticipated expiration: 2003-10-14
Also published as: JPH0621256Y2

Description

[Brief explanation of drawings]

第１図は、この考案を適用したＣＭＯＳデバイ
スのＩＣ内部の回路配置の説明図であり、第２図
は、その接続状態を含めた回路の説明図である。１……Ｐ型のサブストレート、２……ロジツク
回路部、３，１２……Ｎウエル領域、４ａ，５ａ
……ソース領域、４ｂ，５ｂ……ドレイン領域、
７……ゲートライン、８，１６……電源配線のＡ
ｌライン、９，１７……グランド配線のＡｌライ
ン、１０……ＣＭＯＳのチツプ、１１……リニア
回路部。 FIG. 1 is an explanatory diagram of a circuit layout inside an IC of a CMOS device to which this invention is applied, and FIG. 2 is an explanatory diagram of the circuit including its connection state. 1... P type substrate, 2... logic circuit section, 3, 12... N well region, 4a, 5a
... Source region, 4b, 5b ... Drain region,
7...Gate line, 8, 16...Power wiring A
l line, 9, 17... Al line for ground wiring, 10... CMOS chip, 11... linear circuit section.

Claims

[Scope of utility model registration request]

In a CMOS device in which a logic circuit and a linear circuit are integrated into one chip, the power wiring line and constant potential wiring line on the logic circuit side are not connected to the substrate of the chip, and the power wiring line of the logic circuit and the constant potential wiring line are not connected to the substrate of the chip. The power supply wiring line of the linear circuit is internally an independent wiring and can be commonly connected outside the chip, and the constant potential wiring line of the logic circuit and the constant potential wiring line of the linear circuit are internally connected. When the back gate of the transistor of the logic circuit is connected to the constant potential wiring line through the substrate of the chip, the constant potential wiring of the linear circuit The line is connected to the substrate near where the transistor is formed, and the back gate is connected to the constant potential wiring line, and when the back gate of the transistor of the logic circuit is connected to the power supply wiring line via the chip substrate, the A CMO characterized in that a power supply wiring line of a linear circuit is connected to a substrate near where the transistor is formed, and a back gate is connected to the power supply wiring line.
S device.