JPS6426858U - - Google Patents
Info
- Publication number
- JPS6426858U JPS6426858U JP12114187U JP12114187U JPS6426858U JP S6426858 U JPS6426858 U JP S6426858U JP 12114187 U JP12114187 U JP 12114187U JP 12114187 U JP12114187 U JP 12114187U JP S6426858 U JPS6426858 U JP S6426858U
- Authority
- JP
- Japan
- Prior art keywords
- pull
- gate
- turned
- down transistor
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
従来例の回路図である。
１……ＭＯＳ論理集積装置、４……保護ダイオ
ード、５……拡散抵抗、６……寄生ダイオード、
７……プルダウントランジスタ、８……ＭＯＳ論
理回路、９……パルス発生回路、１０……モノマ
ルチバイブレータ。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1...MOS logic integrated device, 4...Protection diode, 5...Diffused resistance, 6...Parasitic diode,
7... Pull-down transistor, 8... MOS logic circuit, 9... Pulse generation circuit, 10... Mono multivibrator.
Claims (1)
のゲート入力保護として、入力端子とＶＤＤ電源
間にダイオードを、また入力端子とゲート間に接
続された拡散抵抗とゲートに接続されたプルダウ
ントランジスタによりプルダウン抵抗を形成して
いるＭＯＳ論理集積装置において、電源投入時に
パルスを発生するパルス発生回路および該パルス
により駆動され、その出力が前記プルダウントラ
ンジスタのゲートに印加されるモノマルチバイブ
レータとを設け、前記プルダウントランジスタが
定常状態においてオンとなり、電源投入後の一定
期間のみオフとなるように、プルダウントランジ
スタのゲート電位を定めていることを特徴とする
ＭＯＳ論理集積装置。 To protect the gate input of the MOS or CMOS transistor in the input stage, a diode is connected between the input terminal and the VDD power supply, and a pull-down resistor is formed by a diffused resistor connected between the input terminal and the gate and a pull-down transistor connected to the gate. A MOS logic integrated device is provided with a pulse generating circuit that generates a pulse when power is turned on, and a mono-multivibrator that is driven by the pulse and whose output is applied to the gate of the pull-down transistor, and when the pull-down transistor is in a steady state. A MOS logic integrated device characterized in that the gate potential of a pull-down transistor is determined so that it is turned on and turned off only for a certain period of time after power is turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12114187U JPS6426858U (en) | 1987-08-06 | 1987-08-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12114187U JPS6426858U (en) | 1987-08-06 | 1987-08-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6426858U true JPS6426858U (en) | 1989-02-15 |
Family
ID=31367882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12114187U Pending JPS6426858U (en) | 1987-08-06 | 1987-08-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6426858U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05302467A (en) * | 1992-04-10 | 1993-11-16 | Hideo Miyazawa | Fitting device for sash |
-
1987
- 1987-08-06 JP JP12114187U patent/JPS6426858U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05302467A (en) * | 1992-04-10 | 1993-11-16 | Hideo Miyazawa | Fitting device for sash |