JPH0174635U - - Google Patents
Info
- Publication number
- JPH0174635U JPH0174635U JP1987169603U JP16960387U JPH0174635U JP H0174635 U JPH0174635 U JP H0174635U JP 1987169603 U JP1987169603 U JP 1987169603U JP 16960387 U JP16960387 U JP 16960387U JP H0174635 U JPH0174635 U JP H0174635U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- supplied
- clock signal
- resistor circuit
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000010354 integration Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
Description
第１図は第１実施例の回路構成説明図、第２図
は従来回路の構成説明図、第３図は第１実施例の
作用説明用特性図、第４図は第２実施例の回路構
成説明図である。
１０……パワーオンリセツト回路、１２……フ
リツプフロツプ、１４……抵抗、１６……コンデ
ンサ、１８……積分回路、２０……ＭＯＳインバ
ータ、２２……ＭＯＳトランジスタ、２４……ク
ロツク発生器、２６……ＭＯＳトランジスタ。
Fig. 1 is an explanatory diagram of the circuit configuration of the first embodiment, Fig. 2 is an explanatory diagram of the configuration of the conventional circuit, Fig. 3 is a characteristic diagram for explaining the operation of the first embodiment, and Fig. 4 is the circuit of the second embodiment. It is a configuration explanatory diagram. 10...Power-on reset circuit, 12...Flip-flop, 14...Resistor, 16...Capacitor, 18...Integrator circuit, 20...MOS inverter, 22...MOS transistor, 24...Clock generator, 26... ...MOS transistor.
Claims (1)
らコンデンサへ抵抗回路を介して充電電流が供給
される積分回路と、 前記コンデンサの充電電圧が所定電圧へ達する
まで、外部の論理回路をリセツトするＭＯＳイン
バータと、 を有し、 前記抵抗回路は、ゲートにクロツク信号が供給
され前記クロツク信号のデユーテイ比に基づいて
導通抵抗が設定されたＭＯＳトランジスタからな
る、 ことを特徴とするパワーオンリセツト回路。[Claims for Utility Model Registration] An integration circuit in which a resistor circuit and a capacitor are connected in series and a charging current is supplied from a power supply to the capacitor via the resistor circuit; a MOS inverter for resetting a logic circuit, and the resistor circuit is comprised of a MOS transistor whose gate is supplied with a clock signal and whose conduction resistance is set based on the duty ratio of the clock signal. Power-on reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169603U JPH0174635U (en) | 1987-11-05 | 1987-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169603U JPH0174635U (en) | 1987-11-05 | 1987-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0174635U true JPH0174635U (en) | 1989-05-19 |
Family
ID=31459813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987169603U Pending JPH0174635U (en) | 1987-11-05 | 1987-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0174635U (en) |
-
1987
- 1987-11-05 JP JP1987169603U patent/JPH0174635U/ja active Pending
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