JPS63187425U - - Google Patents
Info
- Publication number
- JPS63187425U JPS63187425U JP7767387U JP7767387U JPS63187425U JP S63187425 U JPS63187425 U JP S63187425U JP 7767387 U JP7767387 U JP 7767387U JP 7767387 U JP7767387 U JP 7767387U JP S63187425 U JPS63187425 U JP S63187425U
- Authority
- JP
- Japan
- Prior art keywords
- flop
- output terminal
- type flip
- terminal
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の電子回路の１実施例を示す図
、第２図は本考案を強力ライトに実施した構成を
示す図である。
１，１′……センサー、Ｒ１……電流制限抵抗
器、Ｔ１……電源電池のトランジスタ、Ｒ２……
抵抗器、ＩＣ１……ＤタイプフリツプフロツプＣ
ＭＯＳＩＣ、Ｄ……データ入力端子、……出力
端子、Ｓ……セツト端子、Ｒ……リセツト端子、
Ｃ……クロツク入力端子、Ｃ１……コンデンサ、
Ｑ……出力端子、Ｃ２……コンデンサ、Ｒ３……
電流制限抵抗、Ｔ２……トランジスタ、Ｌ……電
球、Ｒ４……抵抗器、Ｂ……電池。
FIG. 1 is a diagram showing one embodiment of an electronic circuit according to the present invention, and FIG. 2 is a diagram showing a configuration in which the present invention is implemented in a powerful light. 1,1'...Sensor, R1 ...Current limiting resistor, T1 ...Power battery transistor, R2 ...
Resistor, IC 1 ...D type flip-flop C
MOSIC, D...Data input terminal,...Output terminal, S...Set terminal, R...Reset terminal,
C...Clock input terminal, C1 ...Capacitor,
Q...Output terminal, C2 ...Capacitor, R3 ...
Current limiting resistor, T2 ...Transistor, L...Light bulb, R4 ...Resistor, B...Battery.
Claims (1)
タで増巾し、そのコレクタに結線された負荷抵抗
に発生した電圧をＤタイプフリツプフロツプＩＣ
のクロツク端子への入力とし、前記Ｄタイプフリ
ツプフロツプＩＣの出力端子とデータ端子を結
線し、Ｑ出力端子と抵抗器を介して第２のトラン
ジスタのベースと結線し、第２のトランジスタの
コレクタに負荷を結線し、Ｄタイプフリツプフロ
ツプＩＣのクロツク端子とグラウンド間及びＱ出
力端子とグラウンド間にコンデンサを結線してな
る電源スイツチ回路。 The minute current flowing through the sensor is amplified by the first transistor, and the voltage generated across the load resistor connected to its collector is transferred to a D-type flip-flop IC.
The output terminal and data terminal of the D-type flip-flop IC are connected, the Q output terminal is connected to the base of the second transistor via a resistor, and the A power switch circuit consisting of a load connected to the collector and a capacitor connected between the clock terminal and ground of a D-type flip-flop IC and between the Q output terminal and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7767387U JPS63187425U (en) | 1987-05-22 | 1987-05-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7767387U JPS63187425U (en) | 1987-05-22 | 1987-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63187425U true JPS63187425U (en) | 1988-11-30 |
Family
ID=30925900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7767387U Pending JPS63187425U (en) | 1987-05-22 | 1987-05-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63187425U (en) |
-
1987
- 1987-05-22 JP JP7767387U patent/JPS63187425U/ja active Pending
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