JPH048127U - - Google Patents
Info
- Publication number
- JPH048127U JPH048127U JP4599890U JP4599890U JPH048127U JP H048127 U JPH048127 U JP H048127U JP 4599890 U JP4599890 U JP 4599890U JP 4599890 U JP4599890 U JP 4599890U JP H048127 U JPH048127 U JP H048127U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- output
- circuit
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Power Sources (AREA)
Description
第1図及び第2図は本考案の一実施例を示し、
第1図は電源投入回路の回路図、第2図は同回路
のタイミングチヤートである。第3図及び第4図
は従来例を示し、第3図は電源投入回路の回路図
、第4図は同回路のタイミングチヤートである。
2……マイクロコンピユータ、3……CPU、
4……第1のJKフリツプフロツプ、7……ポー
ト、10,11……トランジスタ、20……電源
投入回路、21……第2のJKフリツプフロツプ
、22……積分回路、24……電源回路。
1 and 2 show an embodiment of the present invention,
FIG. 1 is a circuit diagram of a power-on circuit, and FIG. 2 is a timing chart of the same circuit. 3 and 4 show a conventional example. FIG. 3 is a circuit diagram of a power-on circuit, and FIG. 4 is a timing chart of the same circuit. 2...Microcomputer, 3...CPU,
4...First JK flip-flop, 7...Port, 10, 11...Transistor, 20...Power supply circuit, 21...Second JK flip-flop, 22...Integrator circuit, 24...Power supply circuit.
Claims (1)
ロツクパルスにより出力Qで電源回路のトランジ
スタをオンとしてマイクロコンピユータを起動す
る電源投入回路に於て、第1並びに第2のJKフ
リツプフロツプからなり、前記第1並びに第2の
JKフリツプフロツプの端子Jを電源へ接続し、
端子Kをアースへ接続し、前記第2のJKフリツ
プフロツプのクロツク端子へマイクロコンピユー
タのCPUのポート出力を接続するとともに、前
記第2のJKフリツプフロツプの出力は、積分
回路を介して前記第1並びに第2のJKフリツプ
フロツプのリセツト端子へ接続し、第1のJKフ
リツプフロツプの出力Qを電源回路に入力し、前
記第1のJKフリツプフロツプのクロツク端子へ
入力されるクロツクパルスによつて、前記ポート
出力に係らず、該出力Qの反転で電源回路のトラ
ンジスタをオンとし、マイクロコンピユータを起
動させることを特徴とするマイクロコンピユータ
の電源投入回路。 In a power-on circuit that turns on a transistor in a power supply circuit with an output Q to start a microcomputer in response to a clock pulse input to a clock terminal of a flip-flop, the power-on circuit consists of a first and a second JK flip-flop, and the first and second JK flip-flops are connected to each other. Connect terminal J of the flip-flop to the power supply,
The terminal K is connected to ground, and the port output of the CPU of the microcomputer is connected to the clock terminal of the second JK flip-flop, and the output of the second JK flip-flop is connected to the first and second clock terminals through an integrating circuit. The output Q of the first JK flip-flop is connected to the reset terminal of the second JK flip-flop, and the output Q of the first JK flip-flop is input to the power supply circuit. A power-on circuit for a microcomputer, characterized in that the inversion of the output Q turns on a transistor of the power supply circuit to start up the microcomputer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4599890U JP2522686Y2 (en) | 1990-04-28 | 1990-04-28 | Microcomputer power-on circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4599890U JP2522686Y2 (en) | 1990-04-28 | 1990-04-28 | Microcomputer power-on circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH048127U true JPH048127U (en) | 1992-01-24 |
JP2522686Y2 JP2522686Y2 (en) | 1997-01-16 |
Family
ID=31560685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4599890U Expired - Lifetime JP2522686Y2 (en) | 1990-04-28 | 1990-04-28 | Microcomputer power-on circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2522686Y2 (en) |
-
1990
- 1990-04-28 JP JP4599890U patent/JP2522686Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2522686Y2 (en) | 1997-01-16 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |