JPS6421527U - - Google Patents

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Publication number
JPS6421527U
JPS6421527U JP11547387U JP11547387U JPS6421527U JP S6421527 U JPS6421527 U JP S6421527U JP 11547387 U JP11547387 U JP 11547387U JP 11547387 U JP11547387 U JP 11547387U JP S6421527 U JPS6421527 U JP S6421527U
Authority
JP
Japan
Prior art keywords
flip
flop
transistor
pulse width
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11547387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11547387U priority Critical patent/JPS6421527U/ja
Publication of JPS6421527U publication Critical patent/JPS6421527U/ja
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の実施例の概略回路図、第2
図は、第1図中の各部の波形図である。 1……トリガ入力端子、2……フリツプフロツ
プリセツト端子(Lレベルでリセツト)、3……
フリツプフロツプ出力端子、4……フリツプフロ
ツプ反転出力端子、5……フリツプフロツプ、6
……フリツプフロツプセツト端子(Lレベルでリ
セツト)、7……抵抗、8……コンデンサ、9…
…ダイオード、10……抵抗、11……トランジ
スタ、12……外部印加電圧端子、13……出力
端子、L……しきい値、14……フリツプフロ
ツプデータ入力端子、15……フリツプフロツプ
クロツク入力端子。
FIG. 1 is a schematic circuit diagram of an embodiment of the present invention;
The figure is a waveform diagram of each part in FIG. 1. 1...Trigger input terminal, 2...Flip-flop preset terminal (reset at L level), 3...
Flip-flop output terminal, 4...Flip-flop inversion output terminal, 5...Flip-flop, 6
...Flip-flop set terminal (reset at L level), 7...Resistor, 8...Capacitor, 9...
...Diode, 10...Resistor, 11...Transistor, 12...Externally applied voltage terminal, 13...Output terminal, L1 ...Threshold value, 14...Flip-flop data input terminal, 15...Flip-flop Program clock input pin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フリツプフロツプ1個、トランジスタ1石を主
要回路構成素子とし、トランジスタのベースに印
加される電圧をパルス幅に変換することを、特徴
としたパルス幅可変回路。
A variable pulse width circuit whose main circuit components include one flip-flop and one transistor, and which converts the voltage applied to the base of the transistor into a pulse width.
JP11547387U 1987-07-27 1987-07-27 Pending JPS6421527U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11547387U JPS6421527U (en) 1987-07-27 1987-07-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11547387U JPS6421527U (en) 1987-07-27 1987-07-27

Publications (1)

Publication Number Publication Date
JPS6421527U true JPS6421527U (en) 1989-02-02

Family

ID=31357163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11547387U Pending JPS6421527U (en) 1987-07-27 1987-07-27

Country Status (1)

Country Link
JP (1) JPS6421527U (en)

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