JPH0328813U - - Google Patents

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Publication number
JPH0328813U
JPH0328813U JP8901989U JP8901989U JPH0328813U JP H0328813 U JPH0328813 U JP H0328813U JP 8901989 U JP8901989 U JP 8901989U JP 8901989 U JP8901989 U JP 8901989U JP H0328813 U JPH0328813 U JP H0328813U
Authority
JP
Japan
Prior art keywords
resistance value
inverter
value resistor
input
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8901989U
Other languages
Japanese (ja)
Other versions
JPH0533056Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8901989U priority Critical patent/JPH0533056Y2/ja
Publication of JPH0328813U publication Critical patent/JPH0328813U/ja
Application granted granted Critical
Publication of JPH0533056Y2 publication Critical patent/JPH0533056Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Oscillators With Electromechanical Resonators (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の実施例を示す発振回路図、
第2図は、他の実施例を示す発振回路、第3図は
、従来の発振回路図を示す。 1……インバータ、4……圧電振動子、10…
…FET、7……高抵抗、8……コンデンサ、9
……低抵抗。
FIG. 1 is an oscillation circuit diagram showing an embodiment of the present invention;
FIG. 2 shows an oscillation circuit showing another embodiment, and FIG. 3 shows a conventional oscillation circuit diagram. 1...Inverter, 4...Piezoelectric vibrator, 10...
...FET, 7...High resistance, 8...Capacitor, 9
...Low resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CMOSインバータの入出力端子間に圧電振動
子を接続し、該インバータの入力端子と電源又は
接地間にFETを接続し、該FETに印加する電
圧によつて発振出力をON、OFFさせる圧電発
振回路において、該インバータの入出力端子に高
抵抗値の抵抗と低抵抗値の抵抗を直列に接続し、
該高抵抗値の抵抗と並列にコンデンサを接続した
ことを特徴とする圧電発振回路。
A piezoelectric oscillation circuit in which a piezoelectric vibrator is connected between the input and output terminals of a CMOS inverter, an FET is connected between the input terminal of the inverter and the power supply or ground, and the oscillation output is turned on and off by the voltage applied to the FET. , a high resistance value resistor and a low resistance value resistor are connected in series to the input/output terminals of the inverter,
A piezoelectric oscillation circuit characterized in that a capacitor is connected in parallel with the high resistance value resistor.
JP8901989U 1989-07-28 1989-07-28 Expired - Lifetime JPH0533056Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8901989U JPH0533056Y2 (en) 1989-07-28 1989-07-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8901989U JPH0533056Y2 (en) 1989-07-28 1989-07-28

Publications (2)

Publication Number Publication Date
JPH0328813U true JPH0328813U (en) 1991-03-22
JPH0533056Y2 JPH0533056Y2 (en) 1993-08-24

Family

ID=31638613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8901989U Expired - Lifetime JPH0533056Y2 (en) 1989-07-28 1989-07-28

Country Status (1)

Country Link
JP (1) JPH0533056Y2 (en)

Also Published As

Publication number Publication date
JPH0533056Y2 (en) 1993-08-24

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