JPS6195127U - - Google Patents
Info
- Publication number
- JPS6195127U JPS6195127U JP17911284U JP17911284U JPS6195127U JP S6195127 U JPS6195127 U JP S6195127U JP 17911284 U JP17911284 U JP 17911284U JP 17911284 U JP17911284 U JP 17911284U JP S6195127 U JPS6195127 U JP S6195127U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- base
- emitter
- input
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
従来のパルス発生回路の回路図である。
１……入力端子、２……第１の入力コンデンサ
、３……第２の入力コンデンサ、４……第１のト
ランジスタ、５……第２のトランジスタ、６，７
……ベース抵抗、８……充放電コンデンサ、９…
…電流源、１０……出力端子。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional pulse generating circuit. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... First input capacitor, 3... Second input capacitor, 4... First transistor, 5... Second transistor, 6, 7
...Base resistance, 8...Charging/discharging capacitor, 9...
...Current source, 10...Output terminal.
Claims (1)
Ｐ型の第１のトランジスタと、同じくベースエミ
ツタ間にベース抵抗を接続したＮＰＮ型の第２の
トランジスタと、入力端子と、前記第１のトラン
ジスタのベースと前記第２のトランジスタのコレ
クタとを接続した接続点と前記入力端子との間に
接続された第１の入力コンデンサと、前記第１の
トランジンスタのコレクタと第２のトランジスタ
のベースとを接続した接続点と前記入力端子との
間に接続された第２の入力コンデンサと、前記第
１のトランジスタのエミツタと第２のトランジス
タのエミツタ間に並列に接続された充放電コンデ
ンサと、この充放電コンデンサに並列に接続され
た電流源と、前記第１のトランジスタのエミツタ
に接続した出力端子とを含むことを特徴とするパ
ルス発生回路。 PN with base resistor connected between base and emitter
A first P-type transistor, a second NPN-type transistor having a base resistor connected between the base and emitter, an input terminal, a base of the first transistor, and a collector of the second transistor are connected. a first input capacitor connected between a connection point and the input terminal; and a first input capacitor connected between the input terminal and a connection point connecting the collector of the first transistor and the base of the second transistor. a second input capacitor; a charge/discharge capacitor connected in parallel between the emitter of the first transistor and the emitter of the second transistor; a current source connected in parallel to the charge/discharge capacitor; and an output terminal connected to the emitter of the first transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17911284U JPS6195127U (en) | 1984-11-26 | 1984-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17911284U JPS6195127U (en) | 1984-11-26 | 1984-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6195127U true JPS6195127U (en) | 1986-06-19 |
Family
ID=30736675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17911284U Pending JPS6195127U (en) | 1984-11-26 | 1984-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6195127U (en) |
-
1984
- 1984-11-26 JP JP17911284U patent/JPS6195127U/ja active Pending
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