JPS6384633U - - Google Patents
Info
- Publication number
- JPS6384633U JPS6384633U JP17983786U JP17983786U JPS6384633U JP S6384633 U JPS6384633 U JP S6384633U JP 17983786 U JP17983786 U JP 17983786U JP 17983786 U JP17983786 U JP 17983786U JP S6384633 U JPS6384633 U JP S6384633U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- signal
- start signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Input From Keyboards Or The Like (AREA)
Description
第１図は本考案の一実施例スタート信号発生回
路のブロツク構成図。第２図は従来のスタート信
号発生回路のブロツク構成図。
１…スタートスイツチ、２，３…Ｄフリツプフ
ロツプ、４…ＲＳフリツプフロツプ、５…ナンド
ゲート、６…ノツトゲート、Ｓ１…スタート信号
、Ｓ２…ストツプ信号、Ｖｃｃ１〜Ｖｃｃ３…定
電圧電源。
FIG. 1 is a block diagram of a start signal generating circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional start signal generation circuit. 1... Start switch, 2, 3... D flip-flop, 4... RS flip-flop, 5... NAND gate, 6... Not gate, S1... start signal, S2 ... stop signal, Vcc1 to Vcc3 ... constant voltage power supply.
Claims (1)
出力するフリツプフロツプ３と、 停止したことを表示するストツプ信号Ｓ２に基
づいて上記フリツプフロツプをクリアするクリア
回路５と を備えたスタート信号発生回路において、 上記スタート信号Ｓ１がリセツト入力に接続さ
れ上記ストツプ信号Ｓ２がセツト入力に接続され
たＲＳフリツプフロツプ４を備え、 上記クリア回路５は、このＲＳフリツプフロツ
プ４の出力および上記ストツプ信号を入力とする
アンド回路を含む ことを特徴とするスタート信号発生回路。[Claims for Utility Model Registration] A flip-flop 3 that outputs a start signal S1 in response to a start command, and a clear circuit 5 that clears the flip-flop based on a stop signal S2 that indicates that it has stopped. The start signal generating circuit includes an RS flip-flop 4 to which the start signal S1 is connected to a reset input and the stop signal S2 is connected to a set input, and the clear circuit 5 receives the output of the RS flip-flop 4 and the stop signal S2. A start signal generation circuit characterized by including an AND circuit that receives a signal as input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17983786U JPS6384633U (en) | 1986-11-21 | 1986-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17983786U JPS6384633U (en) | 1986-11-21 | 1986-11-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6384633U true JPS6384633U (en) | 1988-06-03 |
Family
ID=31123251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17983786U Pending JPS6384633U (en) | 1986-11-21 | 1986-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384633U (en) |
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1986
- 1986-11-21 JP JP17983786U patent/JPS6384633U/ja active Pending