JPS61119430U - - Google Patents
Info
- Publication number
- JPS61119430U JPS61119430U JP65285U JP65285U JPS61119430U JP S61119430 U JPS61119430 U JP S61119430U JP 65285 U JP65285 U JP 65285U JP 65285 U JP65285 U JP 65285U JP S61119430 U JPS61119430 U JP S61119430U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- generating circuit
- level
- inverter
- pulse generating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図の回路の特性図、第３図は従来例を示す
回路図である。
５…信号線、６…第１のインバータ、７…第２
のインバータ、８…第１のパルス発生回路、１１
…第２のパルス発生回路、１４…フリツプフロツ
プ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a characteristic diagram of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional example. 5... Signal line, 6... First inverter, 7... Second
inverter, 8...first pulse generation circuit, 11
...Second pulse generating circuit, 14...Flip-flop.
Claims (1)
し比較的スレツシヨルド電圧の高い第１のインバ
ータと、該第１のインバータの出力が一方のレベ
ルから他方のレベルに変化するときのみパルスを
発生する第１のパルス発生回路と、前記信号線を
入力とし比較的スレツシヨルド電圧の低い第２の
インバータと、該第２のインバータの出力が前記
他方のレベルから一方のレベルに変化するときの
みパルスを発生する第２のパルス発生回路と、前
記第１のパルス発生回路及び第２のパルス発生回
路の出力パルスでセツト及びリセツトされるフリ
ツプフロツプとを備えて成るヒステリシス回路。 A signal line to which a signal is applied, a first inverter that uses the signal line as input and has a relatively high threshold voltage, and generates a pulse only when the output of the first inverter changes from one level to another level. a first pulse generating circuit that uses the signal line as an input and has a relatively low threshold voltage; and a second inverter that generates a pulse only when the output of the second inverter changes from the other level to the one level. A hysteresis circuit comprising a second pulse generating circuit that generates a second pulse, and a flip-flop that is set and reset by the output pulses of the first pulse generating circuit and the second pulse generating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP65285U JPS61119430U (en) | 1985-01-08 | 1985-01-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP65285U JPS61119430U (en) | 1985-01-08 | 1985-01-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61119430U true JPS61119430U (en) | 1986-07-28 |
Family
ID=30472686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP65285U Pending JPS61119430U (en) | 1985-01-08 | 1985-01-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61119430U (en) |
-
1985
- 1985-01-08 JP JP65285U patent/JPS61119430U/ja active Pending
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