JPS63168546U - - Google Patents
Info
- Publication number
- JPS63168546U JPS63168546U JP5941187U JP5941187U JPS63168546U JP S63168546 U JPS63168546 U JP S63168546U JP 5941187 U JP5941187 U JP 5941187U JP 5941187 U JP5941187 U JP 5941187U JP S63168546 U JPS63168546 U JP S63168546U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- reset
- reset signal
- output signal
- predetermined level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000002159 abnormal effect Effects 0.000 claims 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第1図は、本考案の一実施例を示す回路図、第
2図イ乃至ニは本考案の説明に供するための特性
図である。
1…マイコン、2…鋸歯状波発生回路、4…第
1検出回路、6…第2検出回路、8…第1RSフ
リツプフロツプ、9…第2RSフリツプフロツプ
、11…遮断回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2A to 2D are characteristic diagrams for explaining the present invention. DESCRIPTION OF SYMBOLS 1... Microcomputer, 2... Sawtooth wave generation circuit, 4... First detection circuit, 6... Second detection circuit, 8... First RS flip-flop, 9... Second RS flip-flop, 11 ... Cutoff circuit.
Claims (1)
とホールド型リセツト信号とを同時に発生し得る
リセツト信号発生回路であつて、前記クロツク信
号が正常に印加されているとき第1所定レベル以
下の鋸歯状波を発生し、前記クロツク信号が印加
されなくなると前記第1所定レベル以上の出力信
号を発生する鋸歯状波発生回路と、該鋸歯状波発
生回路の出力信号が前記第1所定レベル以上とな
つたことを検出する第1検出回路と、前記出力信
号が第2所定レベル以下となつたことを検出する
第2検出回路と、前記第1検出回路の出力信号に
応じてセツトされるとともに、前記第2検出回路
の出力信号に応じてリセツトされ、間欠型のリセ
ツト信号を発生する第1リセツト信号発生部と、
該第1リセツト信号発生部の出力信号に応じてセ
ツトされるとともに、前記クロツク信号に応じて
リセツトされ、ホールド型のリセツト信号を発生
する第2リセツト信号発生部とを備えたことを特
徴とするリセツト信号発生回路。 A reset signal generating circuit capable of simultaneously generating an intermittent reset signal and a hold type reset signal when a clock signal is abnormal, the circuit generating a sawtooth wave of a level below a first predetermined level when the clock signal is normally applied. a sawtooth wave generation circuit that generates an output signal of the first predetermined level or higher when the clock signal is no longer applied; and an output signal of the sawtooth wave generation circuit that becomes the first predetermined level or higher. a first detection circuit that detects the output signal; a second detection circuit that detects that the output signal becomes lower than a second predetermined level; a first reset signal generating section that is reset in response to the output signal of the detection circuit and generates an intermittent reset signal;
The second reset signal generating section is set in response to the output signal of the first reset signal generating section, and is reset in response to the clock signal to generate a hold type reset signal. Reset signal generation circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5941187U JPH0426916Y2 (en) | 1987-04-20 | 1987-04-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5941187U JPH0426916Y2 (en) | 1987-04-20 | 1987-04-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63168546U true JPS63168546U (en) | 1988-11-02 |
JPH0426916Y2 JPH0426916Y2 (en) | 1992-06-29 |
Family
ID=30890880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5941187U Expired JPH0426916Y2 (en) | 1987-04-20 | 1987-04-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0426916Y2 (en) |
-
1987
- 1987-04-20 JP JP5941187U patent/JPH0426916Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPH0426916Y2 (en) | 1992-06-29 |
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