JPH028232U - - Google Patents

Info

Publication number
JPH028232U
JPH028232U JP1988086206U JP8620688U JPH028232U JP H028232 U JPH028232 U JP H028232U JP 1988086206 U JP1988086206 U JP 1988086206U JP 8620688 U JP8620688 U JP 8620688U JP H028232 U JPH028232 U JP H028232U
Authority
JP
Japan
Prior art keywords
circuit
stage flip
flop
signal
flop circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988086206U
Other languages
Japanese (ja)
Other versions
JPH0735457Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988086206U priority Critical patent/JPH0735457Y2/en
Publication of JPH028232U publication Critical patent/JPH028232U/ja
Application granted granted Critical
Publication of JPH0735457Y2 publication Critical patent/JPH0735457Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Monitoring And Testing Of Transmission In General (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dc Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案による回路動作監視回路の実施
例を示す回路図である。 １……被監視信号、２……第１の２段フリツプ
フロツプ回路、３……タイミング信号、４……第
２の２段フリツプフロツプ回路、５……インバー
タ、６，７……第１および第２の最終段フリツプ
フロツプ出力。 FIG. 1 is a circuit diagram showing an embodiment of a circuit operation monitoring circuit according to the present invention. 1... Signal to be monitored, 2... First two-stage flip-flop circuit, 3... Timing signal, 4... Second two-stage flip-flop circuit, 5... Inverter, 6, 7... First and second flip-flop circuit. Final stage flip-flop output.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被監視信号として正常時は一定間隔のパルスを
出力している回路の動作を監視する回路において
、第１のＮ段のフリツプフロツプ回路と、第２の
Ｎ段のフリツプフロツプ回路とからなり、前記被
監視信号を前記第１のＮ段フリツプフロツプ回路
のセツトまたはリセツト端子に、前記被監視信号
の反転信号を前記第２のＮ段のフリツプフロツプ
回路のセツトまたはリセツト端子に接続するとと
もに前記第１および第２のＮ段のフリツプフロツ
プ回路のクロツク端子に、前記被監視信号のパル
ス間隔のＮ倍のパルス間隔を持つタイミング信号
を入力するようにし、前記第１と第２のＮ段のフ
リツプフロツプ回路の最終段のフリツプフロツプ
出力よりアラーム情報を得るように構成したこと
を特徴とする回路動作監視回路。 A circuit that monitors the operation of a circuit that normally outputs pulses at regular intervals as a signal to be monitored comprises a first N-stage flip-flop circuit and a second N-stage flip-flop circuit. A signal is connected to a set or reset terminal of the first N-stage flip-flop circuit, an inverted signal of the monitored signal is connected to a set or reset terminal of the second N-stage flip-flop circuit, and the first and second flip-flop circuits are connected to each other. A timing signal having a pulse interval N times the pulse interval of the monitored signal is inputted to the clock terminal of the N-stage flip-flop circuit, and the final stage flip-flop of the first and second N-stage flip-flop circuits is connected to the clock terminal of the N-stage flip-flop circuit. A circuit operation monitoring circuit characterized in that it is configured to obtain alarm information from an output.
JP1988086206U 1988-06-29 1988-06-29 Circuit operation monitoring circuit Expired - Lifetime JPH0735457Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988086206U JPH0735457Y2 (en) 1988-06-29 1988-06-29 Circuit operation monitoring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988086206U JPH0735457Y2 (en) 1988-06-29 1988-06-29 Circuit operation monitoring circuit

Publications (2)

Publication Number Publication Date
JPH028232U true JPH028232U (en) 1990-01-19
JPH0735457Y2 JPH0735457Y2 (en) 1995-08-09

Family

ID=31310849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988086206U Expired - Lifetime JPH0735457Y2 (en) 1988-06-29 1988-06-29 Circuit operation monitoring circuit

Country Status (1)

Country Link
JP (1) JPH0735457Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53106158U (en) * 1977-01-31 1978-08-25

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63194418A (en) * 1987-02-09 1988-08-11 Hitachi Ltd Pll circuit
JPS63215139A (en) * 1987-03-04 1988-09-07 Nec Corp Detecting system for fault of signal in balanced double-current interchange

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63194418A (en) * 1987-02-09 1988-08-11 Hitachi Ltd Pll circuit
JPS63215139A (en) * 1987-03-04 1988-09-07 Nec Corp Detecting system for fault of signal in balanced double-current interchange

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53106158U (en) * 1977-01-31 1978-08-25

Also Published As

Publication number Publication date
JPH0735457Y2 (en) 1995-08-09

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