JPS62134149U

JPS62134149U -

Info

Publication number: JPS62134149U
Application number: JP1882086U
Authority: JP
Priority date: 1986-02-14
Filing date: 1986-02-14
Publication date: 1987-08-24

Description

[Brief explanation of the drawing]

第１図は本考案によるウオツチドツグタイマの
望ましい一実施例の概略構成図、第２図は第１図
に示された本考案実施例をやや具体的に示した一
回路構成例の概略構成図、第３図は第２図に示さ
れたウオツチドツグタイマの要部信号波形図、で
ある。図中、１０は本考案にしたがつて構成された全
体としてのウオツチドツグタイマ、１１はクロツ
ク監視回路部、１２はマイクロコンピユータのク
ロツク端子、１３は微分回路、１４は積分回路、
１５はレベル判定回路、１６は微分回路、１７は
リセツトパルス回路、１８はパワーオンリセツト
回路部、１９はマイクロコンピユータのリセツト
入力端子、Ｓ１はリセツトパルス、Ｓ２はクロツ
ク、である。 FIG. 1 is a schematic diagram of a preferred embodiment of a watchdog timer according to the present invention, and FIG. 2 is a schematic diagram of an example of a circuit configuration showing the embodiment of the present invention shown in FIG. 1 in a more concrete manner. The configuration diagram and FIG. 3 are main part signal waveform diagrams of the watchdog timer shown in FIG. 2. In the figure, 10 is a watchdog timer as a whole constructed according to the present invention, 11 is a clock monitoring circuit section, 12 is a clock terminal of a microcomputer, 13 is a differentiating circuit, 14 is an integrating circuit,
15 is a level determination circuit, 16 is a differential circuit, 17 is a reset pulse circuit, 18 is a power-on reset circuit section, 19 is a reset input terminal of the microcomputer, S1 is a reset pulse, and S2 is a clock.

Claims

[Scope of Claim for Utility Model Registration] A power-on reset circuit section that generates a microcomputer reset signal over a certain period of time based on a power-on pulse generated in a power-on pulse generation circuit when the power is turned on; a clock monitoring unit that monitors a clock of the clock, and when an abnormality occurs in the clock, creates a state equivalent to once the power is turned off, and operates the power-on pulse generation circuit;