JPS63143929U

JPS63143929U -

Info

Publication number: JPS63143929U
Application number: JP3494887U
Authority: JP
Priority date: 1987-03-10
Filing date: 1987-03-10
Publication date: 1988-09-21

Description

[Brief explanation of the drawing]

第１図および第２図はこの考案による停電検出
回路の構成を示す図、第３図は従来の停電検出回
路の構成を示す図である。１０…マイクロコンピユータ、１１…ライン同
期回路、１２…波形成形回路、１３…クロツク発
生回路、１４，１７…カウンタ、１５…リセツト
回路、１６…アンド回路。 1 and 2 are diagrams showing the configuration of a power failure detection circuit according to this invention, and FIG. 3 is a diagram showing the configuration of a conventional power failure detection circuit. 10... Microcomputer, 11... Line synchronization circuit, 12... Waveform shaping circuit, 13... Clock generation circuit, 14, 17... Counter, 15... Reset circuit, 16... AND circuit.

Claims

[Claim for Utility Model Registration] A device equipped with a microcomputer that controls various functions, and in which the microcomputer is put into backup mode in the event of a power outage, which includes a line synchronization circuit that sends out a signal synchronized with the power supply frequency, and a reference clock signal. and a counter that counts the reference clock signal of the clock generation circuit, the counter is constantly reset by the output signal of the line synchronization circuit, and when the output signal is not input for a predetermined period of time or more, the counter counts the reference clock signal of the clock generation circuit. A power failure detection circuit is characterized in that it sets a microcomputer to a backup mode, and sets the microcomputer to a normal mode when the output signal is input for a predetermined period or more from the backup mode.