JPH01102942U - - Google Patents

Info

Publication number
JPH01102942U
JPH01102942U JP19795087U JP19795087U JPH01102942U JP H01102942 U JPH01102942 U JP H01102942U JP 19795087 U JP19795087 U JP 19795087U JP 19795087 U JP19795087 U JP 19795087U JP H01102942 U JPH01102942 U JP H01102942U
Authority
JP
Japan
Prior art keywords
circuit
memory
power outage
stop
destruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19795087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19795087U priority Critical patent/JPH01102942U/ja
Publication of JPH01102942U publication Critical patent/JPH01102942U/ja
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のメモリ破壊防止回路の原理ブ
ロツク図、第2図は一実施例の保障回路のブロツ
ク図、第3図は一実施例の電源断検出回路のブロ
ツク図、第4図は一実施例の保障回路の信号波形
図、第5図は従来のメモリ回路のブロツク図、第
6図は従来のメモリ部の動作を説明するための信
号波形図である。 図において、1は情報処理装置、2はメモリ部
、3はメモリ制御回路、4は電源断検出回路、5
は保障回路、6は停止タイミング設定回路、7は
停止信号発生回路、8は整流回路、9は比較回路
、10は電源断信号発生回路、11はクロツク信
号発生回路、12は合成回路、13はカウンタを
示している。
Fig. 1 is a principle block diagram of the memory destruction prevention circuit of the present invention, Fig. 2 is a block diagram of a guarantee circuit of one embodiment, Fig. 3 is a block diagram of a power failure detection circuit of one embodiment, and Fig. 4 is a block diagram of a power failure detection circuit of one embodiment. FIG. 5 is a block diagram of a conventional memory circuit, and FIG. 6 is a signal waveform diagram for explaining the operation of a conventional memory section. In the figure, 1 is an information processing device, 2 is a memory section, 3 is a memory control circuit, 4 is a power-off detection circuit, and 5
6 is a guarantee circuit, 6 is a stop timing setting circuit, 7 is a stop signal generation circuit, 8 is a rectification circuit, 9 is a comparison circuit, 10 is a power-off signal generation circuit, 11 is a clock signal generation circuit, 12 is a synthesis circuit, and 13 is a Shows a counter.

Claims (1)

【実用新案登録請求の範囲】 電源断時のメモリ部2の動作を制御してその破
壊を防止するメモリ破壊防止回路であつて、 電源断を検出する電源断検出回路4と、前記検
出した時間から所定時間遅れたタイミングでメモ
リ部の動作を停止する停止信号を発生する保障回
路5を設け、該保障回路を停止タイミング設定回
路6と停止信号発生回路7とで構成したことを特
徴とするメモリ破壊防止回路。
[Claims for Utility Model Registration] A memory destruction prevention circuit that controls the operation of a memory unit 2 during a power outage to prevent its destruction, comprising a power outage detection circuit 4 that detects a power outage, and the detected time. A memory characterized in that it is provided with a guarantee circuit 5 that generates a stop signal to stop the operation of the memory section at a timing delayed by a predetermined time from the start, and the guarantee circuit is constituted by a stop timing setting circuit 6 and a stop signal generating circuit 7. Destruction prevention circuit.
JP19795087U 1987-12-26 1987-12-26 Pending JPH01102942U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19795087U JPH01102942U (en) 1987-12-26 1987-12-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19795087U JPH01102942U (en) 1987-12-26 1987-12-26

Publications (1)

Publication Number Publication Date
JPH01102942U true JPH01102942U (en) 1989-07-12

Family

ID=31488480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19795087U Pending JPH01102942U (en) 1987-12-26 1987-12-26

Country Status (1)

Country Link
JP (1) JPH01102942U (en)

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