JPH03121452U - - Google Patents

Info

Publication number
JPH03121452U
JPH03121452U JP3121490U JP3121490U JPH03121452U JP H03121452 U JPH03121452 U JP H03121452U JP 3121490 U JP3121490 U JP 3121490U JP 3121490 U JP3121490 U JP 3121490U JP H03121452 U JPH03121452 U JP H03121452U
Authority
JP
Japan
Prior art keywords
output signal
start timing
control output
control start
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3121490U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3121490U priority Critical patent/JPH03121452U/ja
Publication of JPH03121452U publication Critical patent/JPH03121452U/ja
Pending legal-status Critical Current

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  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のバスサイクルを示
す図、第2図は第1図のバスサイクルを設定する
バスサイクル設定レジスタのビツト構成図、第3
図は従来のバスサイクルを示す図である。 201,202,203……制御出力信号、M
REQ,MSTB,IOSTB……制御出力信号
FIG. 1 is a diagram showing a bus cycle according to an embodiment of the present invention, FIG. 2 is a bit configuration diagram of a bus cycle setting register for setting the bus cycle of FIG. 1, and FIG.
The figure is a diagram showing a conventional bus cycle. 201, 202, 203...control output signal, M
REQ, MSTB, IOSTB...Control output signals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部メモリ・外部I/Oへの制御出力信号の制
御開始タイミングをユーザによつて細かく設定す
る機能と、制御開始アチミングを設定するレジス
タとを有し、前記制御出力信号の細かい設定実現
の為に外部供給クロツク周波数を動作周波数の少
なくとも4倍とすることを特徴とするタマイクロ
コンピユータ。
It has a function for the user to finely set the control start timing of the control output signal to external memory/external I/O, and a register to set the control start timing, and is used to realize fine settings for the control output signal. A microcomputer characterized in that an externally supplied clock frequency is at least four times the operating frequency.
JP3121490U 1990-03-27 1990-03-27 Pending JPH03121452U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3121490U JPH03121452U (en) 1990-03-27 1990-03-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3121490U JPH03121452U (en) 1990-03-27 1990-03-27

Publications (1)

Publication Number Publication Date
JPH03121452U true JPH03121452U (en) 1991-12-12

Family

ID=31533956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3121490U Pending JPH03121452U (en) 1990-03-27 1990-03-27

Country Status (1)

Country Link
JP (1) JPH03121452U (en)

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