JPS6216495U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1: Logic control and melody control circuit diagram of the present invention 1, Figure 2: Operation timing diagram for the circuit in Figure 1, Figure 3: Diagram for the circuit in Figure 1 FIG. 4 is an operation timing diagram when the set data for logical regulation is "000" in the circuit of FIG.

Claims (1)

[Scope of utility model registration request] A time standard source, an oscillator that receives a signal from the time standard source and performs oscillation and waveform shaping, a group of counters that divides the output of the oscillator, and data that stores a logical adjustment amount and outputs logical adjustment data. a setting circuit, a timing control circuit that outputs a set timing signal for logical adjustment/acceleration based on a start signal for logical adjustment/acceleration, a melody control circuit that detects a melody start signal and outputs a melody operating signal, and the logical adjustment/acceleration data; Inputting the set timing signal and the melody operating signal, outputting the logical slowing/slowing data at the timing of the set timing signal, and prohibiting output of the logical slowing/fastening data upon receiving the melody operating signal. An electronic timepiece circuit comprising: a gate, and an output of the inhibit gate is input to a set input terminal of the counter group.