JPS6216495U - - Google Patents
Info
- Publication number
- JPS6216495U JPS6216495U JP9784086U JP9784086U JPS6216495U JP S6216495 U JPS6216495 U JP S6216495U JP 9784086 U JP9784086 U JP 9784086U JP 9784086 U JP9784086 U JP 9784086U JP S6216495 U JPS6216495 U JP S6216495U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- melody
- logical
- data
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001133 acceleration Effects 0.000 claims 3
- 230000010355 oscillation Effects 0.000 claims 1
- 238000007493 shaping process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electromechanical Clocks (AREA)
- Electric Clocks (AREA)
Description
第1図・・・本発明の論理緩急、及びメロデイ
制御回路図1、第2図・・・第1図の回路に於け
る動作タイミング線図、第3図・・・第1図の回
路に於ける論理緩急のセツトデータ「000」時
の動作タイミング線図、第4図・・・第1図の回
路に於ける論理緩急のセツトデータ「110」時
の動作タイミング線図。
Figure 1: Logic control and melody control circuit diagram of the present invention 1, Figure 2: Operation timing diagram for the circuit in Figure 1, Figure 3: Diagram for the circuit in Figure 1 FIG. 4 is an operation timing diagram when the set data for logical regulation is "000" in the circuit of FIG.
Claims (1)
けて発振及び波形整形を行なう発振器と、前記発
振器の出力を分周するカウンタ群と、論理緩急量
を記憶し、論理緩急データを出力するデータ設定
回路と、論理緩急のスタート信号により論理緩急
のセツトタイミング信号を出力するタイミング制
御回路と、メロデイスタート信号を検知し、メロ
デイ動作中信号を出立力するメロデイ制御回路と
、前記論理緩急データ、前記セツトタイミング信
号、及び前記メロデイ動作中信号を入力し、前記
セツトタイミング信号のタイミングで前記論理緩
急データを出力し、前記メロデイ動作中信号を受
けて前記論理緩急データの出力を禁示する禁示ゲ
ートとを備え、前記禁止ゲートの出力を前記カウ
ンタ群のセツト入力端子に入力することを特徴と
する電子時計回路。 A time standard source, an oscillator that receives a signal from the time standard source and performs oscillation and waveform shaping, a group of counters that divides the output of the oscillator, and data that stores a logical adjustment amount and outputs logical adjustment data. a setting circuit, a timing control circuit that outputs a set timing signal for logical adjustment/acceleration based on a start signal for logical adjustment/acceleration, a melody control circuit that detects a melody start signal and outputs a melody operating signal, and the logical adjustment/acceleration data; Inputting the set timing signal and the melody operating signal, outputting the logical slowing/slowing data at the timing of the set timing signal, and prohibiting output of the logical slowing/fastening data upon receiving the melody operating signal. An electronic timepiece circuit comprising: a gate, and an output of the inhibit gate is input to a set input terminal of the counter group.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9784086U JPS6227913Y2 (en) | 1986-06-26 | 1986-06-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9784086U JPS6227913Y2 (en) | 1986-06-26 | 1986-06-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6216495U true JPS6216495U (en) | 1987-01-31 |
JPS6227913Y2 JPS6227913Y2 (en) | 1987-07-17 |
Family
ID=30965210
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9784086U Expired JPS6227913Y2 (en) | 1986-06-26 | 1986-06-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6227913Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01154330U (en) * | 1988-04-18 | 1989-10-24 |
-
1986
- 1986-06-26 JP JP9784086U patent/JPS6227913Y2/ja not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01154330U (en) * | 1988-04-18 | 1989-10-24 |
Also Published As
Publication number | Publication date |
---|---|
JPS6227913Y2 (en) | 1987-07-17 |
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