JPH02133029U - - Google Patents
Info
- Publication number
- JPH02133029U JPH02133029U JP4128889U JP4128889U JPH02133029U JP H02133029 U JPH02133029 U JP H02133029U JP 4128889 U JP4128889 U JP 4128889U JP 4128889 U JP4128889 U JP 4128889U JP H02133029 U JPH02133029 U JP H02133029U
- Authority
- JP
- Japan
- Prior art keywords
- baud rate
- circuit
- flip
- comprised
- ring counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Description
第１図は本考案に係るボーレートジエネレータ
を用いてシステムクロツク回路からボーレート用
クロツクを生成し、これを非同期通信用ＩＣに供
給する全体構成ブロツク図、第２図はボーレート
ジエネレータの回路構成を示す図、第３図はその
タイミングチヤートを示す図、第４図は分周回路
を用いて発振回路からボーレート用クロツクを生
成し、これを非同期通信用ＩＣに供給する従来の
全体構成ブロツク図、第５図は前記分周回路の構
成を示す図、第６図はそのタイミングチヤートを
示す図である。
１０……システムクロツク回路、２０……ボー
レートジエネレータ、３０……リングカウンタ、
４５……論理回路。
Figure 1 is a block diagram of the overall configuration of a system that uses the baud rate generator of the present invention to generate a baud rate clock from a system clock circuit and supplies this to an asynchronous communication IC, and Figure 2 is a circuit configuration of the baud rate generator. 3 is a diagram showing its timing chart, and FIG. 4 is a block diagram of a conventional overall configuration in which a baud rate clock is generated from an oscillation circuit using a frequency dividing circuit and is supplied to an asynchronous communication IC. , FIG. 5 is a diagram showing the configuration of the frequency dividing circuit, and FIG. 6 is a diagram showing its timing chart. 10...System clock circuit, 20...Baud rate generator, 30...Ring counter,
45...Logic circuit.
Claims (1)
回路と論理回路との組合せから成り、一定周波数
のクロツク入力信号に対しこれと非整数倍の関係
にあるボーレート用クロツクを生成することを特
徴としたボーレートジエネレータ。 A baud rate generator is comprised of a combination of a ring counter circuit consisting of a flip-flop circuit and a logic circuit, and is characterized in that it generates a baud rate clock that is a non-integer multiple of a constant frequency clock input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4128889U JPH02133029U (en) | 1989-04-07 | 1989-04-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4128889U JPH02133029U (en) | 1989-04-07 | 1989-04-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02133029U true JPH02133029U (en) | 1990-11-05 |
Family
ID=31551828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4128889U Pending JPH02133029U (en) | 1989-04-07 | 1989-04-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02133029U (en) |
-
1989
- 1989-04-07 JP JP4128889U patent/JPH02133029U/ja active Pending
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