JPH02150834U - - Google Patents

Info

Publication number
JPH02150834U
JPH02150834U JP5897989U JP5897989U JPH02150834U JP H02150834 U JPH02150834 U JP H02150834U JP 5897989 U JP5897989 U JP 5897989U JP 5897989 U JP5897989 U JP 5897989U JP H02150834 U JPH02150834 U JP H02150834U
Authority
JP
Japan
Prior art keywords
frequency
signal
circuit
generates
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5897989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5897989U priority Critical patent/JPH02150834U/ja
Publication of JPH02150834U publication Critical patent/JPH02150834U/ja
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の実施例である赤外線リモー
トコントロール送信機のブロツク図である。第2
図は同装置の各部の波形図である。第3図および
第4図は同装置に用いられる倍周回路の構成図お
よび波形図である。第5図は他の実施例に係る倍
周回路の波形図である。 1……クロツク信号発生回路、2……倍周回路
、3……分周回路。
FIG. 1 is a block diagram of an infrared remote control transmitter that is an embodiment of this invention. Second
The figure is a waveform diagram of each part of the device. 3 and 4 are a configuration diagram and a waveform diagram of a frequency doubler circuit used in the device. FIG. 5 is a waveform diagram of a frequency doubler circuit according to another embodiment. 1... Clock signal generation circuit, 2... Frequency doubler circuit, 3... Frequency divider circuit.

Claims (1)

【実用新案登録請求の範囲】 発振信号をシステムクロツクとして供給するク
ロツク信号発生回路と、 前記発振信号を整数倍周して高周波クロツク信
号を発生する倍周回路と、 前記高周波クロツク信号を整数分周して一定周
波数信号を発生する分周回路を備えてなる矩形波
発生回路。
[Claims for Utility Model Registration] A clock signal generation circuit that supplies an oscillation signal as a system clock; a frequency doubling circuit that generates a high frequency clock signal by multiplying the frequency of the oscillation signal by an integer; A rectangular wave generation circuit that includes a frequency divider circuit that rotates the frequency and generates a constant frequency signal.
JP5897989U 1989-05-22 1989-05-22 Pending JPH02150834U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5897989U JPH02150834U (en) 1989-05-22 1989-05-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5897989U JPH02150834U (en) 1989-05-22 1989-05-22

Publications (1)

Publication Number Publication Date
JPH02150834U true JPH02150834U (en) 1990-12-27

Family

ID=31585069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5897989U Pending JPH02150834U (en) 1989-05-22 1989-05-22

Country Status (1)

Country Link
JP (1) JPH02150834U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54100651A (en) * 1978-01-26 1979-08-08 Fujitsu Ltd Pulse-width/pusle-period converter circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54100651A (en) * 1978-01-26 1979-08-08 Fujitsu Ltd Pulse-width/pusle-period converter circuit

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