JPS62177122U - - Google Patents
Info
- Publication number
- JPS62177122U JPS62177122U JP6340986U JP6340986U JPS62177122U JP S62177122 U JPS62177122 U JP S62177122U JP 6340986 U JP6340986 U JP 6340986U JP 6340986 U JP6340986 U JP 6340986U JP S62177122 U JPS62177122 U JP S62177122U
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- signal
- outputs
- pulse
- gate signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は、第１図に示す信号発生回路のタイミングチ
ヤート、第３図は従来の一例を示す回路図、第４
図は、第３図に示す信号発生回路のタイミングチ
ヤートである。
１……パルス発生器、２……ＡＮＤゲート、３
……フリツプフロツプ、４……インバータ、ａ…
…外部ゲート信号、ｂ……パルス信号、ｃ……特
定パルス列信号、ｄ……ゲート信号。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figures are a timing chart of the signal generation circuit shown in Fig. 1, Fig. 3 is a circuit diagram showing a conventional example, and Fig. 4 is a timing chart of the signal generation circuit shown in Fig. 1.
This figure is a timing chart of the signal generating circuit shown in FIG. 3. 1...Pulse generator, 2...AND gate, 3
...Flip-flop, 4...Inverter, a...
...External gate signal, b...Pulse signal, c...Specific pulse train signal, d...Gate signal.
Claims (1)
ルス信号を位相反転させ反転パルス信号を出力す
るインバータと、外部ゲート信号と前記反転パル
ス信号に基づいて前記パルス信号に同期したゲー
ト信号を発生するフリツプフロツプ部と、前記パ
ルス信号と前記ゲート信号との論理積を出力する
論理演算部とを含むことを特徴とする信号発生回
路。 a pulse generator that outputs a pulse signal, an inverter that inverts the phase of the pulse signal and outputs an inverted pulse signal, and a flip-flop unit that generates a gate signal synchronized with the pulse signal based on an external gate signal and the inverted pulse signal. and a logical operation unit that outputs a logical product of the pulse signal and the gate signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6340986U JPS62177122U (en) | 1986-04-25 | 1986-04-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6340986U JPS62177122U (en) | 1986-04-25 | 1986-04-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62177122U true JPS62177122U (en) | 1987-11-10 |
Family
ID=30898607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6340986U Pending JPS62177122U (en) | 1986-04-25 | 1986-04-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62177122U (en) |
-
1986
- 1986-04-25 JP JP6340986U patent/JPS62177122U/ja active Pending
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