JPS6330025U - - Google Patents
Info
- Publication number
- JPS6330025U JPS6330025U JP1986122647U JP12264786U JPS6330025U JP S6330025 U JPS6330025 U JP S6330025U JP 1986122647 U JP1986122647 U JP 1986122647U JP 12264786 U JP12264786 U JP 12264786U JP S6330025 U JPS6330025 U JP S6330025U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock pulses
- gate circuits
- gate
- generate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Description
第1図は本考案の実施例を示す回路図、第2図
は第1図に示された回路の動作を示すタイミング
図である。
1……分周回路、2,3,4,5……NAND
ゲート、10、11,12,13……信号線、1
4,15,16,17……インバータ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. 1... Frequency dividing circuit, 2, 3, 4, 5... NAND
Gate, 10, 11, 12, 13...Signal line, 1
4, 15, 16, 17...inverter.
Claims (1)
からの複数の分周出力に基いてシーケンシヤルに
反復する複数のクロツクパルスを発生する複数の
ゲート回路と、該ゲート回路から前記複数のクロ
ツクパルスを内部回路に供給する複数の信号線と
を備えたクロツクパルス発生回路に於いて、前記
信号線の末端に伝達されたクロツクパルスの各々
を前記複数のゲート回路の各々に印加する帰還回
路を設けたことを特徴とするクロツクパルス発生
回路。 a frequency divider circuit that divides a reference frequency; a plurality of gate circuits that generate a plurality of sequentially repeated clock pulses based on the plurality of divided outputs from the frequency divider circuit; and a plurality of gate circuits that generate the plurality of clock pulses from the gate circuit. In a clock pulse generation circuit equipped with a plurality of signal lines that supply internal circuits, a feedback circuit is provided for applying each of the clock pulses transmitted to the ends of the signal lines to each of the plurality of gate circuits. Characteristic clock pulse generation circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986122647U JPH0633711Y2 (en) | 1986-08-08 | 1986-08-08 | Clock pulse generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986122647U JPH0633711Y2 (en) | 1986-08-08 | 1986-08-08 | Clock pulse generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6330025U true JPS6330025U (en) | 1988-02-27 |
JPH0633711Y2 JPH0633711Y2 (en) | 1994-08-31 |
Family
ID=31013033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986122647U Expired - Lifetime JPH0633711Y2 (en) | 1986-08-08 | 1986-08-08 | Clock pulse generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0633711Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60146315A (en) * | 1984-01-09 | 1985-08-02 | Nec Corp | Clock signal producing system |
JPS62143517A (en) * | 1985-12-18 | 1987-06-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1986
- 1986-08-08 JP JP1986122647U patent/JPH0633711Y2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60146315A (en) * | 1984-01-09 | 1985-08-02 | Nec Corp | Clock signal producing system |
JPS62143517A (en) * | 1985-12-18 | 1987-06-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0633711Y2 (en) | 1994-08-31 |
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