JPH0633711Y2 - Clock pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a clock pulse generation circuit for controlling the operation of a microcomputer or the like.

(B) Conventional technology Generally, a microcomputer operates based on a plurality of clock pulses that are sequentially generated. However, if a weight occurs in each of these clock pulses, the microcomputer malfunctions. Measures are taken to prevent this from happening.

Conventionally, at the gate that generates each clock pulse, the clock pulse generated at that gate is made to rise (or fall) of the next clock pulse.
The weight of the clock was prevented by restricting the clock.

Such a clock pulse generation circuit is disclosed in Japanese Examined Patent Publication No. 61-1360.
It is described in Japanese Patent No.

(C) Problems to be solved by the invention However, the clock pulse output from the conventional clock pulse generation circuit is surely prevented from overlapping, but the signal line for supplying this pulse to the internal circuit There was a case where the pulse overlap occurred at the end of the and the malfunction occurred. The cause is that there is a difference in delay at the terminal due to variations in wiring resistance and capacitance of the respective signal lines, and the difference causes a clock overlap.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and is a frequency dividing circuit for dividing a reference frequency and a plurality of frequency division outputs from the frequency dividing circuit. In a clock pulse generation circuit comprising: a plurality of gate circuits that sequentially and repeatedly generate a clock pulse based on the above; and a plurality of signal lines that supply the plurality of clock pulses to the internal circuit from the gate circuit. By providing a feedback circuit that applies each of the clock pulses transmitted to the terminal to each of the plurality of gate circuits, the overlap of the clock pulses is prevented.

(E) Operation According to the above means, when the clock pulse transmitted at the end of each signal line disappears, the disappearance of the clock pulse is activated by the feedback circuit to activate the gate circuit for generating the next clock pulse. This makes it possible to generate a clock pulse that does not overlap with the previous clock pulse.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. The frequency dividing circuit (1) is a frequency dividing circuit for binary-dividing a reference frequency signal fref output from a crystal oscillation circuit (not shown), and is composed of, for example, two stages of T-FF. 1) divided output φ ₁ and φ ₂ and its inverted output ₁ and
₂ is selectively applied to NAND gates (2) (3) (4) (5). The output terminals of the NAND gates (2), (3), (4) and (5) are respectively connected to the input terminals of the inverters (6), (7), (8) and (9), and the inverters (6), (7) and (8) are connected.
The output terminal of (9) is connected to the signal lines (10) (11) (12) (13). And the inverter (6) (7)
(8) From the output terminals of (9), the divided outputs φ ₁ , ₁ ,
Clock pulse CP ₁ , CP ₂ , CP according to the state of φ ₂ , _2
3 , CP ₄ occurs. Signal line (10) (11) (12) (13)
Are routed to transmit the clock pulses CP ₁ , CP ₂ , CP ₃ and CP ₄ to the internal circuit, and their ends are the inverters (14) (15) (16) (17) which are feedback circuits respectively. Connected to the input of. These signal lines (10) (11) (12) (13) have different internal resistances R ₁ , R ₂ , R ₃ and R ₄ and different stray capacitances C ₁ , C ₂ , C ₃ and C _{4 respectively.} Exists.

Here, the output of the inverter (14) to which the end of the signal line (10) for transmitting the clock pulse CP ₁ is connected is connected to the input of the NAND gate (3) for generating the next clock pulse CP _2. , Similarly, the output of the inverter (15) is NAND
The input of the gate (4), the output of the inverter (16) are connected to the input of the NAND gate (5), and the output of the inverter (17) is connected to the input of the NAND gate (2).

By the way, in the circuit of FIG. 1, a NAND gate (2)
(3) (4) (5) are inverters (14) (15) (16)
Without the feedback of (17), the clock pulses CP ₁ , CP ₂ , CP ₃ and CP ₄ as shown by the broken line in FIG. ₂ should be generated, but the signal lines (10) (11) (12 ) The pulse transmitted to the terminal of (13) is CP ₁ ′, CP ₂ ′, CP ₃ ′ and C in FIG.
Like P ₄ ′, it is delayed by Δt ₁ , Δt ₂ , Δt ₃ and Δt ₄ by resistors R ₁ , R ₂ , R ₃ and R ₄ and capacitors C ₁ , C ₂ , C ₃ and C _4. Therefore, the actual clock pulse CP ₁ , C
P ₂ , CP ₃ and CP ₄ are NAND gates (2) (3) (4)
In (5), inverters (17) (14) (15) (16)
As a result of the rising edge being regulated by the output of, each rising edge has a delay time Δt ₁ , as shown by the solid line in FIG.
The pulse is delayed by Δt ₂ , Δt ₃ and Δt ₄ .

Therefore, for example, the falling edge of the clock pulse CP ₂ ′ transmitted to the end of the signal line (11) and the rising edge of the next clock pulse CP ₃ always coincide with each other, so that the pulses do not overlap.

(G) Effect of the Invention According to the present invention as described above, the pulse at the end of the signal line through which the clock pulse is transmitted does not overlap with the pulse to be generated next, thus preventing malfunction of the microcomputer. However, it has the advantage of improving the reliability of the microcomputer.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. (1) ... divider circuit, (2) (3) (4) (5) ... NAND gate, (10) (11) (12) (13) ... signal line, (14) (1
5) (16) (17) ... Inverter.

Claims (1)

[Scope of utility model registration request] 1. A frequency divider circuit for dividing a reference frequency signal, and a plurality of frequency division outputs to which a plurality of frequency division outputs from the frequency divider circuit are selectively applied and which repeats an operation of successively and sequentially generating a plurality of clock pulses. A gate circuit, and a plurality of signal lines for supplying the plurality of clock pulses from the plurality of gate circuits into the circuit to be controlled, wherein the plurality of signal lines are provided inside the circuit. Only the transmission delay time caused by the wiring resistance and stray capacitance of the plurality of signal lines before the plurality of clock pulses are transmitted from the plurality of gate circuits to the inside of the circuit to be controlled when being routed. In order to close the plurality of gate circuits, an output terminal of the gate circuit that generates the immediately preceding clock pulse and a clock pulse that immediately follows the plurality of gate circuits are generated. Is connected in series with the signal line for transmitting the immediately preceding clock pulse between the input terminals of the gate circuit, the output terminal of the gate circuit for generating the last clock pulse, and the first clock pulse for generating the first clock pulse. A plurality of feedback circuits connected in series with the signal line transmitting the last clock pulse are provided between the input terminals of the gate circuit to prevent the plurality of clock pulses from overlapping in the circuit to be controlled. A clock pulse generation circuit characterized by: