JPS63253715A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To obtain a biphase clock signal not overlapped with each other independently of the presence of wire capacitance difference by providing a circuit varying the capability of a clock driver. CONSTITUTION:The titled circuit consists of a timing generator 101, a clock driver 102, a delay comparison circuit 103 comparing a delay between an inverted clock signal, the inverse of CLKA and a clock signal CLK1 with a prescribed reference pulse width and outputting a high level only when the delay value exceeds a reference pulse width and a holding circuit 14 holding the output and turning on a buffer 14 placed in parallel with the output buffer 13 of the timing generator 101. Thus, the clock generated by the timing generator 101 is driven by the buffers 13, 14 to cancel the delay in the wire capacitance and the clock without delay to the clock CLKA is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock generation circuit, and particularly to a clock generation circuit that can prevent one-phase clocks from overlapping when a clock generation circuit is configured using an automatic layout method. Regarding circuits.

[Conventional technology]

Conventionally, this type of clock generation circuit consists of only a timing generator and a clock driver.

FIG. 4 is a circuit diagram of an embodiment of a conventional clock generation circuit.

In this embodiment, a delay is generated only at the falling edge of the clock signal CLK as an input, and two inverted clock signals CLKA and CLKB of the same frequency that do not overlap are generated.
It consists of a timing generator 101 that generates phase clocks, and a clock driver 102 that receives the CLKA and CLKB as input and supplies clock signals to the entire chip.

FIG. 5(a) is a timing diagram in the clock generation circuit. By inputting the clock signal CLK, the timing generator 101 outputs the inverter 2 at the falling edge.
-5 generates a delay time T1 and inverters 8-11 generate a delay time T2, and two-phase clocks CLKA and CLKB of the same frequency that do not overlap are generated.

The clock driver 102 receives the above-mentioned CLKA and CLKB as inputs and receives clock signals CLK1 . C
I'm making LK2.

FIG. 3 is a layout diagram of the above clock generation circuit laid out on the IC chip 100.

Since the clock driver 102 supplies a clock signal to the entire chip, the final stage buffer 17゜20 must have a large dimension and increase its driving ability, so it becomes a source of noise and does not affect the internal area. Therefore, the timing generator 101 is created for this purpose.
The wiring capacitances C1 and C2 between the clock driver 102 and the clock driver 102 were values that could not be ignored.

Furthermore, if there is a condition of C1>>C2 between the wiring capacitances C1 and 02, as shown in FIG. As a result, an overlap T' occurred between CLKI and CLK2.

For this reason, in the conventional clock generation circuit, the wiring capacitances C1 and C2 between the timing generator 101 and the clock driver 102 had to be designed to be equal in layout.

[Problem that the invention seeks to solve]

In the conventional clock generation circuit described above, the wiring capacitance C1,
C2 must match.

However, when designing a layout using an automatic layout method, it is impossible to perfectly match the wiring capacitance of two wires, and when using a conventional clock generation circuit, manual intervention is required. There was a drawback that it was not possible.

An object of the present invention is to provide a clock generation circuit that does not cause overlap of output clocks regardless of the presence or absence of a difference in wiring capacitance between a timing generator and a clock driver.

[Means for solving problems]

The clock generation circuit of the present invention includes: a timing generator that generates two-phase clocks of the same frequency using a one-phase clock input from the outside; a clock driver that receives the two-phase clock signal generated by the timing generator; a circuit that detects a delay between the outputs of the timing generator and the clock driver;
and a circuit that turns on a buffer placed in parallel with the buffer that generates the clock for the timing generator only when the delay is longer than a certain period.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In this embodiment, in addition to the timing generator 101 and the clock driver 102, a delay comparison unit that compares the delay between CLKA and CLKI with a predetermined reference pulse width and outputs a high level only when the delay value exceeds the reference pulse width. The wiring capacitance C1 in this embodiment is composed of a circuit 103 and a holding circuit 104 that holds the output of this delay comparison circuit 103 and turns on a buffer 14 placed in parallel with the output buffer 13 of the timing generator 101. If C2 becomes 01>>C2,
As in the conventional example, an overlap T' shown in FIG. 5(b) occurs between the output clocks CLKI and CLK2.

FIG. 3 is a timing diagram according to the present embodiment. When clocks overlap, the delay comparison circuit 103
is the NAND gate circuit 25. The reference pulse width (shown in FIG. 3B) synchronized with the falling edge of CLKA generated by the inverters 21 to 24 and the NOR gate circuit 26
The delay value T of CLKA and CLKI detected by
d (shown in the third IJB) and the NAND gate circuit 27.
The inverter 28 compares both pulse widths and outputs a high level (as shown in FIG. 3C) during the period when the delay value Td exceeds the reference pulse width.

The high level signal output by the delay comparison circuit 103 is transmitted to the NOR gate circuit 32.3 of the holding circuit 104.
3 is held by the latch and turns on the buffer 14.

As a result, since the tarock generated by the timing generator 101 is driven by the buffer 13.14, the delay Td due to the wiring capacitance is canceled and the CL
A clock with no delay with respect to KA can be obtained (Fig. 3C)
(shown in LKI').

Resistor 29 inside the holding circuit 104. Capacitor 31 and inverter 31 form a power-on reset circuit.

When the power is turned on, the inverter 31 outputs a high level for a certain period of time to determine the initial state of the latch by the NOR gate circuits 32 and 33. In addition, the delay comparison circuit 10
3 and holding circuit 104 in the CLK2 generation section,
Even if the wiring capacitances C1 and C2 meet the condition of C2>>CI, overlapping of output clocks can be prevented.

〔Effect of the invention〕

As described above, in the clock generation circuit of the present invention, by having a circuit that varies the driver capability of the clock driver, it is possible to obtain two-phase clock signals that do not overlap with each other regardless of the presence or absence of wiring capacitance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a layout diagram of a clock generation circuit on a chip, FIG. 3 is a timing diagram of an embodiment of the present invention, and FIG. 4 is a conventional example. The circuit diagram and FIGS. 5(a) and 5(b) are timing diagrams in a conventional example. 100... IC chip, 101... Timing generator, 102... Clock driver, 103...
- Delay comparison circuit, 104...holding circuit. , 1ζ Agent Patent Attorney Susumu Uchihara, - ′-(6

Claims (1)

[Claims] a timing generator that generates a two-phase clock of the same frequency based on a one-phase clock signal input from the outside;
A clock driver inputs the two-phase clock signal generated by this timing generator, and only when the delay between the outputs of the timing generator and clock driver becomes larger than a predetermined value, the drive ability of the output signal of the timing generator is changed. What is claimed is: 1. A clock generation circuit comprising means for increasing the clock frequency.