JP3080038B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a plurality of output buffers.

[0002]

2. Description of the Related Art Generally, an output buffer circuit of a semiconductor integrated circuit drives a load capacitance such as a parasitic capacitance of its own transistor and a connection capacitance between an output terminal and an external element in addition to an external element as a load. Therefore, it has a large gain, and a current of several tens mA flows instantaneously to the elements of the output buffer circuit when charging and discharging the load capacitance. As a result, the power supply noise in the semiconductor integrated circuit fluctuates instantaneously and the input threshold value of each element also fluctuates.
There is a problem that the semiconductor integrated circuit malfunctions.

Conventionally, various proposals have been made to prevent malfunctions of elements due to power supply noise during simultaneous operation of a plurality of such output buffer circuits. For example, JP-A-63-39
In the conventional semiconductor integrated circuit described in Japanese Patent Publication No. 212, simultaneous operation of a plurality of output buffer circuits is avoided by providing a delay circuit on at least one input side of the plurality of output buffer circuits.

Referring to FIG. 4, which shows a block diagram of a conventional semiconductor integrated circuit, this conventional semiconductor integrated circuit responds to the supply of the internal signal S101 and an internal circuit 100 for outputting internal signals S101 and S102 of the semiconductor integrated circuit. An output buffer circuit 101 for outputting an output signal O101 to an output terminal T101, a delay circuit 103 for delaying the internal signal S102 by a predetermined time and outputting a delay signal D102, and an output terminal T102 in response to the supply of the delay signal D102. And an output buffer circuit 102 that outputs an output signal O102.

[0005] The output buffer circuit 101 comprises inverters I101 and I102 connected in series and an inverter I103 comprising a PMOS transistor Q101 and an NMOS transistor Q102.

The output buffer circuit 102 comprises inverters I201 and I202 connected in series and an inverter I203 comprising a PMOS transistor Q201 and an NMOS transistor Q202. The delay circuit 103 includes four inverters I301 to I304 connected in series.

Next, the operation of the conventional semiconductor integrated circuit will be described with reference to FIG. 4 and FIG. 5 which shows each signal waveform in a waveform diagram. First, the internal circuit 101 changes the internal signals S101 and S102 which change at the same timing. Is output. When the internal signals S101 and S102 transition from the L level to the H level at the same timing, the inverters I101 and I10
2, I201, I202 and each delay time of the inverters I301 to I304 constituting the delay circuit 6 are represented by ΔT. After the internal signal S102 transitions from the L level to the H level, the potential of the node N102 changes from the L level after 6ΔT. Transition to the H level. On the other hand, the potential of the node N201 changes from the L level to the H level 2ΔT after the transition of the internal signal S1.

That is, even if the potentials of the internal signals S101 and S102 change at the same timing, the output terminal T10
1, the potentials of the output signals O101 and O102 of T102 do not change at the same time, and 4ΔT after the potential change of the output signal O101.
Later, the potential of the output signal O102 changes. As a result, the load currents of the output buffer circuits 101 and 102 are temporally dispersed, so that power supply noise in the semiconductor integrated circuit can be reduced and malfunction of the internal circuit elements can be prevented.

[0009]

In the conventional semiconductor integrated circuit described above, the delay control is performed independently for each output buffer circuit, so that the delay is canceled by the timing skew of each delay circuit and internal signal. In this case, there is a disadvantage that the effect cannot be obtained.

In addition, since a uniform delay time is assigned to each output buffer regardless of a change in the internal signal, it is necessary to design in consideration of all the combinations of the above changes, and it is necessary to determine an output buffer circuit in which the internal signal changes simultaneously. Therefore, there is a disadvantage that it is necessary to insert a delay circuit suitable for each of them and circuit design is difficult.

An object of the present invention is to provide a semiconductor integrated circuit which prevents malfunctions of internal circuit elements due to power supply noise during simultaneous operation of output buffer circuits.

[0012]

According to the present invention, there is provided a semiconductor integrated circuit including first to Nth (positive integers of 2 or more) output buffer circuits for outputting corresponding output signals in response to supply of input signals, respectively. A semiconductor integrated circuit comprising:
Each said input signal and this output buffer circuit, second N
An input signal control circuit for receiving a control signal for controlling the latch of the input signal, latching the input signal in response to the control of the control signal, and outputting the latched latch signal as the output signal; An input detection circuit for detecting an input of the control signal and outputting an input detection signal having a predetermined time width; receiving the control signal and delaying the control signal by a predetermined delay time to generate a delay control signal; and a control signal output circuit which outputs a supply control output signal by a logical operation result of the signal and the input detection signal as a control signal of another output buffer circuit, the first to N
Of the N-th output buffer circuit as the control signal.
The control output signals of the first to (N-1) th output buffer circuits are
And the first to Nth output
And a control circuit for delaying the output of the output buffer circuit to which the control output signal is supplied until the output of the output signal is completed.

[0013]

FIG. 1 is a block diagram showing an output buffer circuit which characterizes an embodiment of the present invention. Referring to FIG. 1, an output buffer circuit of a semiconductor integrated circuit according to this embodiment shown in FIG. An input signal control circuit 1 that receives a supply of an input signal S and a control signal CS and outputs a latch signal SL;
A buffer circuit 2 that outputs an output signal O in response to the supply of the latch signal SL; an input signal detection circuit 3 that detects an input of an input signal S and outputs a detection signal SD;
And a control signal output circuit 4 for receiving the supply of the control signal and outputting a control output signal CO.

The input signal control circuit 1 outputs an inverted input signal SB by inverting the input signal S and an inverter I11 having a delay value of Δt1, and a negative logic for latching the inverted input signal SB and outputting a latch signal SL. And a gate input latch L11.

The buffer circuit 2 includes an inverter I21 for inverting the latch signal SL and outputting an output signal O.

The input signal detection circuit 3 includes inverters I31 and I32 which are connected in series and have a delay value of Δt1 and Δt2, respectively, and output a delay signal D1, a delay signal D1 having a delay value of Δt3 and an input signal S. And an EXNOR gate EX31 for taking an exclusive NOR of the above and outputting a delay signal SD.

The control signal output circuit 4 latches the control signal CS and outputs a latch signal Q and outputs a negative logic clock D-type flip-flop F41. The control signal output circuit 4 latches the control signal CS and outputs a latch signal LC. Latch signal L
Inverter I which inverts C and outputs inverted latch signal CB
NAND gate G which takes the NAND of the delay signal SD and the inverted latch signal CB and outputs a control output signal CO
41.

Next, the operation of the output buffer circuit of the present embodiment will be described with reference to FIG. 1. In the output buffer circuit of the present embodiment, the input signal control circuit 1 outputs the output of another output buffer circuit. In addition to controlling the transmission of the input signal S to the output signal O according to the control signal CS, the input signal detection circuit 3 detects a change in the input signal S and generates a new control output signal CO together with the control signal CS. Supply to other output buffer circuits.

First, in the input signal control circuit 1, the inverter I11 inverts the input signal S, outputs an inverted input signal SB, gives a delay value of Δt1, and supplies it to the latch L11. The latch L11 latches the inverted input signal SB when the input control signal CS is at the L level, and supplies the latch signal SL to the buffer circuit 2. Inverter I2 of buffer circuit 2
1 inverts the latch signal SL and outputs the output signal O via the terminal T3. In the input signal detection circuit 3, the inverters I31 and I32 give a delay value of Δt1 + Δt2 to the input signal S and output a signal D1, and the EXNOR gate EX31
To supply. The EXNOR gate EX31 performs an exclusive NOR operation of the signal D1 and the input signal S, detects a rise or fall of the input signal S, detects a delay value of Δt3 from the input signal S, and has a negative width of Δt1 + Δt2. The logic delay signal SD is output.

The control signal output circuit 4 latches the level of the control signal CS in the flip-flop F41 at the falling transition of the delay signal SD output from the input signal detection circuit 3, and outputs a latch signal Q. That is, the flip-flop F4
1 indicates that when the level of the control signal CS is L level, the latch L41 is latched by the L level latch signal Q,
If it is at the H level, the latch L41 is set to the through state by the latch signal Q at the H level, and the latch signal LC of the control signal CS is supplied to the inverter I41. Inverter I41
Is the inverted latch signal CB in response to the supply of the latch signal LC.
To the NAND gate G41. NAND gate G
41 performs a NAND operation on the inverted latch signal CB and the delay signal SD, and outputs the control output signal CO via the terminal T4.

Next, referring to FIG. 2 showing a block diagram of the interconnection of a plurality of output buffer circuits, the semiconductor integrated circuit of this embodiment shown in FIG.
0, 20 and 30. For convenience of description, the components of the output buffer circuits 10, 20, and 30 each having a single digit are represented by 10s, 20s, and 30s, respectively. For example, the input signal control circuit of the output buffer
And

The input terminal T11 of the output buffer circuit 10 is connected to the input terminal TI10, and the input signal S1 is supplied to the input signal control circuit 11 via these terminals TI10 and T11.
It is supplied to the input signal detection circuit 13. The output terminal T1
3 is connected to the output terminal TO10 and outputs an output signal O1. The control input terminal T12 is connected to the control signal output terminal T34 of the output buffer circuit 30, and receives the signal CO3 as the control signal CS1. The control signal output terminal T14 is connected to the control input terminal SD2 of the output buffer circuit 20, and supplies the control output signal CO1.

Similarly, the input terminal T21 of the output buffer circuit 20 is connected to the input terminal TI20, and the input signal S2 is supplied to the input signal control circuit 21 and the input signal detection circuit 23 via these terminals TI20 and T21. . The output terminal T23 is connected to the output terminal TO20 and the output signal O2
Is output. As described above, the control input terminal SD2 receives the signal C from the output buffer circuit 10 as the control signal CS2.
Receive supply of O1. The control signal output terminal T24 is connected to the control input terminal T32 of the output buffer circuit 30 and supplies a control output signal CO2.

Similarly, the input terminal T31 of the output buffer circuit 30 is connected to the input terminal TI30, and the input signal S3 is supplied to the input signal control circuit 31 and the input signal detection circuit 33 via these terminals TI30 and T31. . The output terminal T33 is connected to the output terminal TO30 and the output signal O3
Is output. As described above, the control input terminal SD2 receives the signal C from the output buffer circuit 20 as the control signal CS3.
Receive supply of O2. The control signal output terminal T34 is connected to the control input terminal T12 of the output buffer circuit 10 and supplies a control output signal CO3.

The operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to FIGS. 1 and 2 and FIG. 3 showing the operation waveforms of the respective parts in a time chart. First, the operation is input to the input terminal TI10 of the output buffer circuit 10. The input signal S1 is
Assume that the rising transition occurs at time T1. The output buffer circuit 10 receives the signal S delayed by Δt1 by the inverter I11 of the input signal control circuit 11 in response to the supply of the input signal S1.
B1 is generated, and the signal SB1 is output from the output terminal TO10 as the output signal O1 via the latch L11, the inverter I21, and the terminal T13.

The input signal detection circuit 13 responds to the supply of the input signal S1 by a delay time width (Δt1) delayed by Δt3.
+ Δt2) is generated and output. At this time,
Control output detection circuit 14 at the falling edge of signal SD1
Flip-flop F41 latches the L level of the input control signal CS1 to generate an L level latch signal Q1. The latch L41 enters the latch state in response to the supply of the L level latch signal Q1 and outputs the latch signal LC1, and the inverter I41 inverts the latch signal LC1 and outputs the H level of the signal CB1. The transmission of the input control signal CS1 is interrupted. Since the signal CB1 is at the H level, the NAND gate G41 outputs an inverted signal of the signal SD1 as the control output signal CO1 and supplies the inverted signal to the output buffer circuit 20 as the input control signal CS2.

Here, it is assumed that the input signal S2 slightly delayed from the time T1 is supplied to the input terminal TI20 of the output buffer circuit 20.

The output buffer circuit 20 operates in the same manner as the aforementioned output buffer circuit 10 in response to the supply of the input signal S2, and generates the signals SB2 and SD2. However, the latch L11 of the input signal control circuit 21 outputs the H level input control signal CS2 at the falling edge time Ta of the signal SB2.
, The signal SB2 is cut off by the latch L11. Therefore, output signal O corresponding to signal SB2 is output.
2 is not output to the output terminal TO20. Next, at time Tb
, The input control signal CS2 falls and the latch L
11 enters a through state, and supplies a latch signal SL2 corresponding to the signal SB2 to the inverter I21.
Outputs an output signal O2 corresponding to the signal SL2 to an output terminal TO2.
Output to 0.

At the falling edge of the signal SD2, the flip-flop F41 of the control output detection circuit 24 latches the H level input control signal CS2 and outputs a latch signal Q2. The latch L41 enters a through state in response to the supply of the signal Q2, and the latch signal L corresponding to the input control signal CS2.
C2 is supplied to the inverter I41. Inverter I41
Is a signal CB delayed by Δt4 corresponding to the latch signal LC2.
2 is supplied to the NAND gate G41. The NAND gate G41 outputs a control output signal CO2 as a result of a NAND logical operation of the signals SD2 and CB2, and supplies it as a control input signal CS3 of the output buffer circuit 30.

The output buffer circuit 30 operates in the same manner as the above-described output buffer circuit 20 in response to the supply of the input signal S3, and generates the signals SB3 and SD3. Output terminal TO30
Outputs an output signal O3 corresponding to the input signal S3 supplied at a time Tc when the control input signal CS3 falls slightly after the time T1.

The control output signal CO of the output buffer circuit 30
3 is supplied as an input control signal CS1 of the output buffer circuit 10. As described above, since the latch L41 of the input control circuit 11 at this time is in the latched state, the signal CS1 is supplied.
1 is cut off and is not output as the control output signal CO1.

As a result, the control signal CS is transmitted to the control signal input terminal T2, which is sequentially connected to the control signal input terminal T2, starting from the output buffer circuit in which the input signal S is input to the signal input terminal T1. The output signal O is output from the output terminal T3 at the time when the signal CS is shifted to the H level by the delay time in each output buffer circuit.

The H-level delay time of the control signal CS is equal to the control output signal CO output from the output buffer circuit of the preceding stage by a unit delay time Δt4 of the inverter I41 every time the output signal passes through one output buffer circuit. To increase,
Even if the input signals S of the output buffer circuits change almost simultaneously, the output signals O are separated by the width Δt4.

As described above, in this embodiment, the operation in the case where the output buffer circuit 10 is the starting point has been described. However, the case where the output buffer circuit 20 is the starting point as shown at time T2 can be similarly described.

In the present embodiment, the connection of three output buffer circuits has been described. However, the present invention is not limited to this, and the same operation can be performed for four or more interconnections.

[0036]

As described above, in the semiconductor integrated circuit of the present invention, each of the plurality of output buffer circuits latches an input signal in response to control of a control signal and outputs the latched input signal as an output signal. An input detection circuit that detects an input of an input signal and outputs an input detection signal having a predetermined time width; and a logical operation of the delay control signal obtained by delaying the control signal by a predetermined delay time and the input detection signal A control signal output circuit for supplying a control signal as a control signal for another output buffer circuit according to the result, and controlling the output of the other output buffer circuit to be delayed by the control output signal until the output of the output signal is completed. Even if the input signal of another output buffer circuit changes at substantially the same timing as the change of the input signal of any output buffer circuit, the other output buffer For changing the output signal of the circuit,
There is an effect that simultaneous operation of the output buffer circuit is suppressed, and malfunction due to simultaneous operation can be prevented.

Further, since the state of the input signal of each output buffer circuit is individually monitored and the control signal of the other output buffer circuit is output, the designer can adjust the output buffer circuit in accordance with the timing of the input signal. There is an effect that the effect of preventing malfunction due to simultaneous operation can be obtained without considering the use location.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an output buffer circuit characterizing one embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a block diagram showing an example of interconnection of a plurality of output buffer circuits in the semiconductor integrated circuit according to the present embodiment.

FIG. 3 is a time chart illustrating an example of an operation in the semiconductor integrated circuit of the present embodiment.

FIG. 4 is a block diagram illustrating an example of a conventional semiconductor integrated circuit.

FIG. 5 is a time chart showing an example of an operation in a conventional semiconductor integrated circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input signal control circuit 2 Buffer circuit 3 Input signal detection circuit 4 Control signal output circuit 10, 20, 30, 101, 102 Output buffer circuit 100 Internal circuit 103 Delay circuit F41 Flip-flop G41 NAND gate I11, I21, I31, I32, I41 Inverter L11, L41 Latch EX31 EXNOR gate

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (2)

(57) [Claims] 1. A corresponding response to the supply of each input signal
The first to Nth (two or more positive integers)
A semiconductor integrated circuit comprising : (a) an output buffer circuit, wherein each of the first to Nth output buffer circuits receives the input signal and a control signal for controlling a latch of the input signal, and controls the control signal. An input signal control circuit that latches the input signal in response to the input signal and outputs the latched latch signal as the output signal; and an input detection that detects an input of the input signal and outputs an input detection signal having a predetermined time width. A circuit for receiving the control signal, delaying the control signal by a predetermined delay time to generate a delay control signal, and controlling another output buffer circuit based on a logical operation result of the delay control signal and the input detection signal. A control signal output circuit that outputs a control output signal supplied as a signal, and a control signal for each of the first to Nth output buffer circuits.
To control the Nth, 1st to N-1st output buffer circuits.
Connect to supply a control output signals, respectively, each of the output buffer circuit of the first to N is a supply destination of <br/> output buffer circuit of the control output signal to the output of said output signal is terminated A semiconductor integrated circuit characterized in that output is controlled to be delayed. 2. An input signal control circuit comprising: a first inverter for inverting the input signal to output an inverted input signal; and a negative logic gate input for latching the inverted input signal and outputting the latched signal. A first latch, wherein the input detection circuit is connected in series, has a second delay value, outputs a first delay signal having a first delay value as a whole, and a second delay value. An EXNOR gate for performing an exclusive NOR operation on the first delay signal and the input signal to output a second delay signal, wherein the control signal output circuit latches the control signal and outputs a first signal.
A flip-flop of a negative logic clock that outputs a latch control signal of a first latch control signal, a second latch that latches the control signal in response to the supply of the first latch control signal, and outputs a second latch control signal; A fourth inverter that inverts a second latch control signal and outputs an inverted latch signal of a third delay value, and performs a NAND operation on the second delay signal and the inverted latch signal to generate the control output signal. NAN to output
2. The semiconductor integrated circuit according to claim 1, further comprising a D gate.