JPH0431618Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a system clock generation circuit that is built into a one-chip microcomputer or the like and generates system clock pulses for controlling operation.

(B) Prior Art A semiconductor integrated circuit that performs digital processing, such as a one-chip microcomputer, generally operates based on a plurality of clock pulses, and has a built-in circuit that generates the plurality of clock pulses.

Conventionally, a system clock generation circuit for a one-chip microcomputer has a frequency divider circuit that divides a reference clock pulse obtained by a crystal or ceramic oscillator circuit, and a frequency divider circuit that inputs multiple divided outputs of the frequency divider circuit to generate multiple clock pulses. It consists of a gate circuit that creates the system clock. The system clocks are designed so that they do not overlap each other. That is, the rising or falling edge of a system clock pulse is regulated by the rising edge or falling edge of another system clock pulse, thereby preventing the system clock pulse from becoming too heavy.

The above technique is described in detail in Japanese Patent Publication No. 13601/1983.

(c) Problems to be solved by the invention However, the conventional system clock pulse generation circuit prevents the system clock pulse from becoming heavy by directly transmitting the system clock pulse output from the generation circuit to the generation circuit. Since the rise or fall is regulated by feedback to the input, at the end of the signal line routed from the system clock generation circuit to the inside of the semiconductor integrated circuit,
Differences in internal resistance and stray capacitance of each signal line cause a difference in pulse delay, which can result in heavier pulses and cause malfunctions.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points. The purpose of this is to prevent system clock pulses from becoming too heavy and eliminate malfunctions by feeding back the end of the extended signal line to the input of the system clock generation circuit.

(E) Effect According to the above-mentioned means, a system clock pulse is supplied to each circuit inside the semiconductor integrated circuit from a signal line provided around the circuit, but the system clock pulse is delayed further than the delay of the system clock pulse. Since the clock pulse is generated at the end of the signal line, the most delayed system clock pulse regulates the rise or fall of other system clock pulses, thereby preventing the system clock pulses from becoming heavier.

(F) Embodiment The figure is a circuit diagram showing an embodiment of the present invention. In the figure, 1 is a frequency dividing circuit, 2 is a gate circuit, 3 is a signal line, and 4 is a semiconductor integrated circuit chip.

The frequency dividing circuit 1 is a frequency dividing circuit which inputs a reference clock pulse φ generated by an oscillation circuit (not shown) and divides the frequency to 1/4, and is made up of two stages of T-FFs connected together. The gate circuit 2 inputs the outputs Q ₁ , ₁ , Q ₂ , ₂ of each stage of the frequency divider circuit 1 and generates and outputs four types of system clock pulses CP ₁ to CP ₄ . ₁ , ₁ , _Q2 , ₂ are selectively applied, and inverters 6 each connected to the output of the NAND gate 5, and the output of each inverter 6 is connected to the system clock pulse _CP1 ~ It becomes CP ₄ . Also, inverter 6
Each output is connected to one end of a signal line 3, and each signal line 3 is routed around the chip 4. The end of each signal line 3 that went around the chip 4 is
It is extended to the vicinity of the gate circuit 2, and the inverter 7
are respectively connected to the inputs of the NAND gates 5 of the gate circuit 2 via the gate circuit 2. That is, the terminal signal of the system clock pulse CP ₄ is applied to the input of the NAND gate ₅ which creates the system clock pulse CP 1, and creates the system clock pulse CP ₂ .
The terminal signal of the system clock pulse CP ₁ is applied to the input of the NAND gate 5, and so on.

In the figure, a resistor 8 connected in series with the signal line 3 represents the internal resistance of the signal line 3, and a capacitor 9 represents the stray capacitance of the signal line 3. Also, 10,
Reference numeral 11 denotes an internal circuit provided in the chip 4 of the semiconductor integrated circuit, and each internal circuit 10, 11 receives a system clock pulse CP via a supply line 12 located at the shortest distance from the signal line 3 provided around the chip 4. ₁ ~ _CP4
is supplied. This supply line 12 also has an internal resistance 13
and stray capacitance 14, but these are much smaller than the resistor 8 and capacitor 9 of the signal line 3.

By providing the signal line 3 as shown in the figure, the system clock pulse CP ₁ ~
Since the delay of CP ₄ is larger than the delay of any part inside the chip 4 such as internal circuits 10 and 11,
By regulating the rising edge of the next system clock pulse using the system clock pulses CP ₁ to _{CP 4} at the end, overlapping of the pulses can be completely prevented.

(g) Effects of the invention As described above, according to the invention, the weight of the system clock pulse is completely eliminated, so malfunctions of semiconductor integrated circuits such as one-chip microcomputers are eliminated, and reliability is greatly improved. It will improve.

[Brief explanation of the drawing]

The figure is a circuit diagram showing an embodiment of the present invention. 1... Frequency dividing circuit, 2... Gate circuit, 3... Signal line, 4... Semiconductor integrated circuit chip.

Claims (1)

[Scope of utility model registration request] A frequency divider circuit that divides the frequency of a reference clock pulse, a gate circuit that inputs multiple divided outputs of the frequency divider circuit and creates multiple system clock pulses that do not overlap each other, and a system from the gate circuit. In a system clock generation circuit for a semiconductor integrated circuit comprising a plurality of signal lines for supplying clock pulses to various parts within the integrated circuit, the plurality of signal lines extend around a chip of the semiconductor integrated circuit. A system clock generation circuit for a semiconductor integrated circuit, characterized in that a terminal thereof is connected to the gate circuit.