JPH0223703A - Oscillation control circuit - Google Patents

Abstract

PURPOSE:To reduce consumption power by leading the output of FF which is set by a stop signal in an integrated to outside, controlling the external clock signal through the use of the stop signal, and reducing a current which is caused by an external clock signal when oscillation stops. CONSTITUTION:A signal inputted to the input terminal X1 of an oscillator is furthermore inverted through an invertor 1, and a phase becomes equal to that of the input terminal X2 of the oscillator, whereby the signal is inputted to a NOR gate 5. Since the input terminal 7 of the oscillator is in an L level, the external clock signal can be used as an internal clock signal CLK through the NOR gate 5. When the internal stop signal STOP is set to an H level here, FF6 is set and an oscillation control signal 7 comes to the H level. The oscillation control signal 7 is inputted to a NOR gate 8 and an OR gate through an oscillation control output terminal PRT. The input terminal X1 of the oscillator is fixed to the L level, and the input terminal X2 of the oscillator to the H level, and the internal clock signal CLK is stopped. Thus, the current caused by the external clock signal is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit incorporating an oscillation circuit, and sometimes to control of the oscillation circuit.

[Conventional technology]

Conventionally, the oscillation circuit of integrated circuits such as microprocessors has
There is an oscillation circuit having the configuration shown in FIG.

The area inside the dotted line shows the inside of the integrated circuit, particularly the oscillation circuit.

RES is an input terminal into which an external reset signal is input. R.E.
Although not shown, SIN is a reset signal to other circuits inside the integrated circuit, and is a signal of an external reset signal input terminal RES. 5TOP is an internal stop signal, which is an input signal from inside the integrated circuit. 6 is a flip-flop, Q is the output of the flip-flop 6, S is a set signal input of the flip-flop 6, and an internal stop signal 5TOP is input thereto.

R is a reset signal input of the flip-flop 6 and is connected to an external reset signal input terminal 'RES.

7 is an oscillation control signal and is the output Q of the flip-flop 6. 5 is a NOR gate to which the oscillation control signal 7 is input. 3
is an inverter and inputs the oscillation control signal 7. Xl and X
2 is an oscillator input terminal of the integrated circuit. 1 is an inverter which operates as an inverting amplifier, and its input terminal is connected to the oscillator input terminal X1, and its output terminal is connected to the oscillator input terminal X2. 2
is an FET that operates as a feedback resistor for the inverter 1, and has a gate connected to the output terminal of the inverter 3, a source connected to the oscillator input terminal X2, and a drain connected to the oscillator input terminal X1. G
ND is ground. 4 is an FET whose gate is connected to the oscillation control signal 7, whose source is connected to the ground GND, and whose drain is connected to the oscillator input terminal X1.

The other input terminal of NOR gate 5 is the oscillator input terminal
Connect with 2. CLK is an internal clock signal and outputs the output of the NOR gate 5 as a clock signal to the inside of the integrated circuit. 14 is a crystal oscillator, one terminal of which is connected to the oscillator input terminal X1, and the other terminal connected to the oscillator input terminal X2. 15 is a capacitor, one terminal of which is connected to the oscillator input terminal X1, and the other terminal connected to the ground GND. 1
6 is a capacitor, one terminal of which is connected to the oscillator input terminal X2, and the other terminal connected to the ground GND.

Next, the operation of this circuit will be explained. When the external reset signal input terminal RES is set to H level, the flip-flop 6 is reset and the oscillation control signal 7 is set to L level.

This turns FET4 off and FET2 on.

FET2 serves as a feedback resistor for inverter 1, and the circuit oscillates with a crystal oscillator connected to inverter 1 and FET2, and an internal clock signal CLK is obtained.

To stop the oscillation, the internal stop signal 5TOP is set to H level to set the flip-flop 6, and the oscillation control signal 7 is set to H level. FET4 is on,
FET2 is turned off, oscillator input terminal X1 is set to L level by FET4, oscillation is stopped, and internal clock signal CLK is stopped.

The above is a case where a crystal oscillator is connected to the oscillator input terminals XI and X2, but there are cases where it is desired to operate a microprocessor or the like using a clock signal supplied from the outside. In an integrated circuit, it is desirable to have a small number of external terminals, and therefore the external clock signal is input to the oscillator input terminals Xi, X2 without providing a separate terminal for the external clock signal.

FIG. 4 shows an external clock circuit when an external clock signal is used in the conventional oscillation circuit shown in FIG. For connection to the integrated circuit, the crystal oscillator connected to the oscillator input terminals Xi and X2 in FIG. 3 is removed, and the external clock circuit shown in FIG. 4 is connected to the oscillator input terminals Xi and X2. Fourth
In the figure, φ is an input terminal into which an external clock signal is input. 17 is an inverter whose input terminal is connected to an external clock input terminal φ. 18 is an inverter, the input end of which is connected to the output end of the inverter 17. The output terminal of inverter 18 is connected to oscillator input terminal X1, and the output terminal of inverter 17 is connected to oscillator input terminal X2. Since the other circuits are the same as those in FIG. 3, their explanation will be omitted.

In order to obtain the internal clock signal CLK using an external clock signal, the flip-flop 6 is reset by setting the external reset signal input terminal RES to the H level, the oscillation control signal 7 is set to the L level, and the FET 4 is turned off. Become. In this state, the external clock signal input to the oscillator input terminal X1 is inverted through the inverter 1, becomes in phase with the oscillator input terminal X2, and is input to the NOR gate 5.

Since the oscillation control signal 7 is at L level, the internal clock signal C
LK is obtained.

If the internal clock signal CLK is to be stopped now, the internal stop signal 5TOP is set to H level, the flip-flop 6 is set, and the oscillation control signal 7 is set to H level. FET4 is turned on and outputs an L level to the oscillator input terminal X1. Oscillation control signal 7 is at H level, so NOR
The output of gate 5 becomes L level, and internal clock signal C
LK is fixed at L level and internal clock signal CLK is stopped.

[Problem to be solved by the invention]

In the conventional oscillation circuit described above, when an external clock circuit is connected, if the oscillation circuit is stopped by an internal stop signal, the external clock signal input to the oscillator input terminal X1 does not stop, and FET4 is turned on. , when the external clock signal is high and high, a large current flows through FET4, increasing power consumption, and due to the same cause, latch-up in the CMO8 integrated circuit destroys the integrated circuit. That being said, there are drawbacks.

[Means to solve the problem]

an oscillation circuit having at least an oscillation stop control terminal; a memory circuit set by the first signal and cleared by the second signal; and an output of the memory circuit connected to the oscillation stop control terminal of the oscillator; It has an integrated circuit led out to a terminal, and a circuit outside the integrated circuit that controls clock signal input from outside the integrated circuit using a signal from an external terminal of the integrated circuit.

[Example 1] The present invention will be described below based on Examples. Figure 1 shows
1 is an oscillation control circuit diagram showing an embodiment of the present invention. FIG.

The area inside the dotted line shows the inside of the integrated circuit, particularly the oscillation circuit.

RES is an input terminal into which an external reset signal is input. R.E.
Although not shown, SIN is a reset signal to other circuits inside the integrated circuit, and is a signal of an external reset signal input terminal RES. 5TOP is an internal stop signal, which is an input signal from inside the integrated circuit. 6 is a flip-flop, Q is the output of the flip-flop 6, S is a set signal input of the flip-flop 6, and an internal stop signal 5TOP is input thereto.

R is a reset signal input of the flip-flop 6 and is connected to an external reset signal input terminal RES.

7 is an oscillation control signal and is the output Q of the flip-flop 6. PRT is an output terminal to the outside of the integrated circuit, which is connected to the output Q of the flip-flop 6, and outputs an oscillation control signal 7 to the outside of the integrated circuit.
I will provide a. 5 is a NOR gate to which the oscillation control signal 7 is input. 3 is an inverter to which the oscillation control signal 7 is input. Xl and X2 are the oscillator input terminals of the integrated circuit. 1 is an inverter that operates as an inverting amplifier, and its input terminal is connected to the oscillator input terminal X1, and its output terminal is connected to the oscillator input terminal X2. 2 is an FET which operates as a feedback resistor for the inverter 1, and has a gate connected to the output side of the inverter 3, a source connected to the oscillator input terminal X2, and a drain connected to the oscillator input terminal X1. GND is ground. 4 is an FET whose gate is connected to the oscillation control signal 7, whose source is connected to the ground GND, and whose drain is connected to the oscillator input terminal X1. The other input terminal of NOR gate 5 is connected to oscillator input terminal X2. CLK
is an internal clock signal and outputs the output of the NOR gate 5 as a clock signal to the inside of the integrated circuit. 8 is a NOR gate whose input terminal is connected to the oscillation control output terminal PRT. 9 is an OR gate whose input terminal is the oscillation control output terminal P
Connect to RT. φ is an input terminal into which an external clock signal is input, and is connected to the other input terminal of the NOR gate 8 and the other input terminal of the OR gate 9, respectively. The output terminal of the NOR gate 8 is connected to the oscillator input terminal X1 and the OR gate 9
The output terminal of is connected to the oscillator input terminal X2.

Next, the operation of this embodiment will be explained. When the external reset signal is set to H level, the flip-flop 6 is reset. Therefore, the oscillation control signal 7 becomes L level and passes through the oscillation control output terminal PRT.
R game) 8. It is input to OR gate 9. This results in
An external clock signal is input to the oscillator input terminal X2, and an inverted signal of the external clock signal is input to the oscillator input terminal X1. The signal input to the oscillator input terminal
2 and is input to the NOR gate 5. Since the oscillation control signal 7 is at L level, the external clock signal can be used as the internal clock signal CLK through the NOR gate 5.

When it is desired to stop the internal clock signal CLK, the flip-flop 6 is set by setting the internal stop signal 5TOP to H level, the oscillation control signal 7 becomes H level, and the oscillation control signal 7 is output via the oscillation control output terminal PRT. It is input to the NOR gate 80R gate 9, the oscillator input terminal Xi is fixed at L level, the oscillator input terminal X2 is fixed at H level, and the internal clock signal CLK can be stopped.

At the oscillator input terminals Xi and X2, the signal levels of the external circuit of the integrated circuit and the internal circuit of the integrated circuit are in phase.

[Embodiment 2] FIG. 2 shows another embodiment of the oscillation control circuit of the present invention. The difference from the embodiment shown in FIG. 1 is the external clock signal control section outside the integrated circuit. Hereinafter, parts that are different from the embodiment shown in FIG. 1 will be explained.

10 is an inverter, the input end of which is connected to an external clock input terminal φ. 11 is a FET whose source is connected to the output terminal of the inverter 10 and whose drain is connected to the oscillator input terminal X1. 12 is a FET, the source of which is connected to the external clock input terminal φ, and the drain connected to the oscillator input terminal
2. 13 is an inverter whose input terminal is connected to the oscillation control output terminal PRT, and whose output terminal is connected to the gate of FET II and the gate of FET 12.

When the external reset signal terminal RES is set to the fifth level, the flip-flop 6 is reset. Therefore, the oscillation control signal 7 becomes L level, passes through the oscillation control output terminal PRT and the inverter 13, and the H level is applied to the gate of FET 11.12, FET 11.12 is turned on, and the external clock signal is sent to the oscillator input terminal X2. The inverted signal is applied to the oscillator input terminal X1 to obtain the internal clock signal CLK.

To stop the internal clock signal CLK, the internal stop signal 5TOP is set to H level, the flip-flop 6 is set, and the oscillation control signal 7 is set to H level. The oscillation control signal 7 enters the inverter 13 via the oscillation control output terminal PRT, and the inverter 13 becomes L level. Therefore, FET11 and F'ET12 are turned off,
The external clock signal applied to the oscillator input terminals XI, X2 is cut off, and the oscillator input terminals Xi, X2 enter a high impedance state. Since the H level of the oscillation control signal 7 is input to the NOR gate 5, the internal clock signal CLK is fixed at the L level, and the internal clock signal CLK can be stopped.

At the oscillator input terminal X1, the signal level of the external circuit of the integrated circuit is high impedance, and the signal level of the internal circuit of the integrated circuit is L level. Oscillator input terminal
2, the signal level of the external circuit of the integrated circuit is high impedance, and the signal level of the internal circuit of the integrated circuit is H level.

〔Effect of the invention〕

As described above, the present invention provides the flip-flop 6 set by the stop signal 5TOP inside the integrated circuit.
By leading the output to the outside and using that signal to control the external clock signal, it is possible to reduce the current caused by the external clock signal when oscillation is stopped and reduce power consumption. Also, since no current flows into the oscillator input terminals XI and X2 due to the external clock signal, the CM
O8 integrated circuits do not cause latch-up and are effective in preventing damage to the integrated circuits.

FIG. 3 shows a conventional oscillation circuit using a crystal oscillator, and FIG. 4 shows a conventional external clock circuit.

In the figure, 1, 3, 10, 13, 17.18 are inverters, 2, 4, 11.12 are FETs, 5.8 is a NOR gate, 9 is an OR gate, 6 is a flip-flop, and 7 is an oscillation control signal. show. RES is an external reset signal input terminal. RESIN is an internal reset signal. 5TO
P is an internal stop signal. In the flip-flop 6, Q is an output, S is a set signal input, and R is a reset signal input. PRT supplies an oscillation control signal 7 at its output terminal. Xl and X2 are oscillator input terminals.

φ is an external clock signal input terminal. CLK is an internal clock signal. GND is ground.

Agent: Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the oscillation control circuit of the present invention, and FIG. 2 shows a second embodiment of the oscillation control circuit of the present invention. =14-

Claims (1)

[Claims] an oscillation circuit having at least an oscillation stop control terminal; a memory circuit set by the first signal and cleared by the second signal; and an output of the memory circuit connected to the oscillation stop control terminal of the oscillator; An oscillation control circuit comprising: an integrated circuit led out to a terminal; and a circuit outside the integrated circuit that controls a clock signal input from outside the integrated circuit using a signal from an external terminal of the integrated circuit.