JPH0619206Y2 - Integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an integrated circuit composed of a complementary metal oxide semiconductor (hereinafter referred to as CMOS), and more particularly to an integrated circuit having an oscillation circuit built therein.

[Conventional technology]

Generally, this kind of oscillator circuit is composed of an inverter and a feedback resistor, and operates as a crystal oscillator circuit by connecting a crystal oscillator, and is mainly built into an information processing device such as a microcomputer, and is a reference for the operation of the information processing device. To generate a clock signal. In recent years, these information processing apparatuses are generally composed of a CMOS integrated circuit in order to reduce power consumption, and so-called standby for stopping the oscillation operation of the oscillation circuit in order to further reduce power consumption. Some have functions. FIG. 3 shows an example of a conventional oscillator circuit having means for realizing the standby function. In FIG. 3, 1 is a CMOS integrated circuit such as a microcomputer having an oscillation circuit built therein, 2 is a P-channel MOS transistor (hereinafter referred to as “PMOS”) Q ₁ and N-channel MOS transistor (hereinafter referred to as “NMOS”) Q ₂ 3 is a feedback resistor, 18 is a standby signal line, 19 is an inverter, 19 is an inverter, 8 and 20 are both transfer gates, 4 is an inverter 2, a feedback resistor 3, an inverter 19, and transfer gates 8 and 20. 2 is an internal main circuit such as a microcomputer that uses the clock signal generated by the oscillation circuit 4, 6 and 7 are external connection terminals, 13 is a crystal oscillator, and 14 and 15 are capacitors. In this case, the oscillator circuit 4, the crystal oscillator 13, and the capacitors 14 and 15 constitute a crystal oscillator circuit. Since the standby signal line 18 is normally at the Low potential, the transfer gate 20 is in a non-conducting state (hereinafter referred to as an off state), and the transfer gate 8 is in a conducting state (hereinafter referred to as an on state), so that the inverter 2 outputs the same. Is fed back to the input by the feedback resistor 3 and can operate as a crystal oscillation circuit. In the standby state, the transfer gate 20 is turned on and the transfer gate 8 is turned off because the standby signal line 18 is at a high potential. Therefore, the feedback by the feedback resistor 3 is not performed in the inverter 2, and its input is connected to GND, so that the output of the oscillation circuit 4 becomes High potential and its oscillation is stopped. Since this standby signal is not directly related to the contents of this description, it will be treated as a low potential in the following, and will be omitted in the following description unless particularly required.

Next, FIG. 4 shows an example of the configuration in which the clock signal used in the internal main circuit 5 is input from the outside. In this case, the crystal oscillator is not necessary, and since the inverter 2 is used as an input buffer, The clock signal is supplied to the terminal 7. In Figure 4, 16 at the output stage of the inverter included in the external circuit for generating an external clock, PMOS Q ₇
And it consists of NMOS Q _8. Now, assuming that in the inverter 16 only the NMOS Q ₈ is in the ON state and the external signal connected to the terminal 7 is at the Low potential, the inverter 2
In, only the PMOS Q ₁ is turned on and the High potential is output. However, since the input and output of the inverter 2 are connected by the feedback resistor 3 at this time, at this time, Low
The input of the inverter 2 which should be a potential rises to some extent and becomes Hi
The output of the inverter 2, which should be at the gh potential, drops to some extent and enters an equilibrium state. At this time, depending on the degree of decrease in the output potential of the inverter 2, the logic element that receives the output of the inverter 2 in the internal main circuit 5 may not be accurately recognized as the High potential and may malfunction. Where NMOS
The ON resistance value of Q _{8 in} the equilibrium state is R ₈ · PMOS Q ₁
When the resistance value in the equilibrium state of R ₁ is R ₁ , the on-resistance value of the transfer gate 8 is R _t , and the resistance value of the feedback resistor 3 is R, the input of the inverter 2 which should be Low potential is V _IL , and the High potential is Letting V _OH be the output of the inverter 2 which should be, it is expressed as follows.

If only PMOS · Q ₇ in the inverter 16 to the contrary the external signal connected to the terminal 7 in the ON state is assumed to be High potential, as in the previous examples, due to the influence of the feedback resistor 3, High The input of the inverter 2, which should be at the potential, decreases to some extent, and the output of the inverter 2, which should be at the low potential, rises to some extent and enters a balanced state. At this time, depending on the degree of decrease in the output potential of the inverter 2, the logic element that receives the output of the inverter 2 in the internal main circuit 5 becomes Low.
There is a possibility of malfunction because it cannot be accurately recognized as a potential. Here at equilibrium of PMOS · _{Q 7,} the resistance value of the on-resistance value in the equilibrium state of the _{R 7 · NMOS · Q 2 R} 2,
The input of the inverter 2 which should be high potential is V _IH , and L
The output of the inverter 2, which should be at the ow potential, is V _OL , hereinafter R _t
And R are represented as follows, assuming the same as the previous example.

In order to prevent the malfunction due to the influence of the feedback resistor 3 as described above, conventionally, an external inverter such as the inverter 10 and the inverter 11 shown in FIG. 5 has been required.

The description of FIG. 5 will be given below. The same reference numerals as those in FIG. 4 denote the same circuits. Reference numeral 10 denotes an inverter composed of PMOS.Q ₃ and NMOS.Q ₄ , both of which have a large drive capacity, that is, a small on-resistance. In FIG. 5, an inverter 10 is connected to the outside of the CMOS integrated circuit 1 so as to be in parallel with the inverter 2 built in the oscillation circuit 4, and the PMOS Q ₁ and NM indirectly constituting the inverter 2 are formed.
By improving the drive capability of each transistor of the OS Q ₂ , the reduction of the output potential amplitude due to the influence of the feedback resistor 3 in the inverter 2 is suppressed. this is,
In the second formula introduced above, the output V _{OH of the} inverter 2, which should be originally at high potential, becomes close to V _DD as the ON resistance value R ₁ at the time of equilibrium of the PMOS Q ₁ decreases. Also, it can be proved that the output V _{OL of the} inverter 2 which should be originally at the low potential becomes close to zero as R ₂ which is the on-resistance value of the NMOS Q ₂ in equilibrium decreases in the fourth equation. . Further, when the driving capability of each of the transistors of the PMOS Q ₇ and the NMOS Q ₈ which constitute the inverter 16 in FIG. 4 described above is low and the on resistance thereof is high, R ₈ increases in the first equation. as a result,
The input V _{IL of the} inverter 2 which should originally be at a low potential rises to some extent, and in the second equation, R ₇ increases, and as a result, the input V _{IH of the} inverter 2 which is supposed to be at a high potential decreases to some extent. . In this way, when the drive capability of each of the PMOS Q ₇ and NMOS Q ₈ transistors forming the conventional inverter 16 is not sufficient, the output potential amplitude of the inverter 2 is affected by the feedback resistor 3 as described above, and the output potential amplitude of the inverter 16 is It is also affected by the lack of drive capacity, which further reduces the possibility of malfunction and increases the possibility of malfunction. Therefore, conventionally, as shown in FIG. 5, the output of the inverter 16 had to be input to the inverter 11 having a sufficient drive capacity, and then the output had to be input to the terminal 7.

[Problems to be solved by the invention]

In the conventional oscillation circuit built in the CMOS integrated circuit, there is no particular problem when the crystal oscillation circuit is configured by connecting the crystal oscillator and the output thereof is used as the clock signal in the internal circuit. However, when the external clock is input as the input buffer using the inverter in the oscillator circuit and the output is used as the clock signal in the internal circuit, the output level amplitude of the oscillator circuit decreases due to the influence of the feedback resistor built in the oscillator circuit. The internal circuit using the output may malfunction. Therefore, in the past, this was improved by connecting an inverter with a large drive capacity to the outside. On the other hand, the inverter elements are ICs (Integr
ated Curcuit) is marketed, if you need such an inverter, you need space to place this package. The package generally has to be mounted on a printed circuit board to increase the space of the printed circuit board, which is disadvantageous in terms of cost and also has the drawback of increasing the cost of purchasing the IC. Therefore, the present invention is to solve the above-mentioned drawbacks and to provide an integrated circuit incorporating an oscillation circuit capable of obtaining a normal operation without connecting an inverter externally even when an external clock is used.

[Means for Solving the Problems]

To this end, the integrated circuit of the present invention specifies either a first operation mode in which an oscillation element is connected to obtain an oscillation signal or a second operation mode in which a signal is obtained based on a clock signal from the outside. The switch in the feedback loop is controlled according to whether it is in the standby state or the normal state in the first operation mode.
In the second operation mode, the opening is performed regardless of any state.

〔Example〕

Next, the present invention will be described with reference to the drawings. 1 and 2 show an embodiment of the present invention. FIG. 1 corresponds to FIG. 3 of the conventional example, and the same reference numerals as those in FIG. 3 denote the same circuits. Reference numeral 9 is an external terminal, 17 is a 2-input NOR, and one of the gates is connected to the standby signal line 18 and the other is connected to the external terminal 9. As shown in FIG. 1, when this oscillator circuit is used as a crystal oscillator circuit, by keeping the external terminal 9 at a low potential, the output of the inverter 2 is connected to its input via the feedback resistor 3 and crystal oscillation is possible. Becomes

Next, FIG. 2 corresponds to FIG. 4 of the conventional example, and the same reference numerals as those in FIGS. 4 and 1 denote the same circuits. As shown in FIG. 4, when this oscillator circuit is used as a kind of input buffer circuit and an external clock is input, the external terminal 9 is set to High.
By keeping the potential, the output of the NOR gate 17 becomes Low potential, and the transfer gate 8 is turned off. Therefore, since the feedback resistor 3 is removed from the inverter 2,
The input level of the inverter 2 is completely controlled by the voltage level of the external terminal 7. In other words, since it is possible to prevent the output potential amplitude of the inverter 2 from decreasing due to the influence of the feedback resistor 3, normal operation is realized without the need for external inverters such as the inverter 10 and the inverter 11 shown in FIG. I can.

[Effects of the Invention] As is clear from the above description, according to the present invention, even when an external clock is input to an oscillator circuit with a built-in feedback resistor, feedback is performed without adding an external inverter as in the past. The reduction in output level amplitude due to the effect of resistance can be completely eliminated. Therefore, the effect is large in terms of cost and space as compared with the conventional one. Further, in particular, when a circuit for controlling the action of the feedback resistor such as the transfer gate 8 in FIG. 3 is already built in as a means having a standby function, the present invention can be realized by simply operating this control circuit from the outside. Since it can be realized, only a slight change in the circuit can be performed, so that the manufacturing cost is not particularly increased. Therefore, the effect on the reduction of the final cost as a total is very large.

[Brief description of drawings]

1 and 2 are circuit diagrams showing an oscillator circuit according to the present invention. FIG. 3, FIG. 4, and FIG. 5 are circuit diagrams showing a conventional oscillator circuit. 1 ... CMOS integrated circuit incorporating an oscillation circuit, 2, 1
0, 11, 16 ... Inverter, 3 ... Feedback resistor, 4 ...
… Oscillation circuit, 5 …… Internal main circuit, 6,7,9,12 ……
Terminals, 8, 20 ... Transfer gates, 13 ... Crystal oscillators, 14, 15 ... Capacitors, 17 ... NOR
Circuit, 18 ... Standby signal line, Q ₁ , Q ₃ , Q ₅ ,
Q ₇ ... P-channel MOS transistor (PMO
S), Q ₂ , Q ₄ , Q ₆ , Q ₈ ... N-channel MO
S transistor (NMOS).

Claims (1)

[Scope of utility model registration request] 1. A first terminal, a second terminal and a third terminal, and the first terminal.
An inverter having an input and an output connected to the second terminal and a second terminal, a series circuit of a feedback resistor and a switch means connected between the input and output of the inverter, and a control signal, which specifies a normal operation state. And a control means for closing the switch means when the standby state is specified and for holding the output of the inverter at a predetermined potential level when designating a standby state. An oscillation signal is generated at the output of the inverter by an oscillation element connected outside the integrated circuit between the first and second terminals in the mode, and integrated in the first terminal in the second operation mode. In an integrated circuit that generates a clock signal at the output of the inverter based on a clock signal supplied from the outside of the circuit, Wherein the level of the third terminal first
Or the second operation mode is specified, and when the level of the third terminal specifies the first operation mode, the opening / closing of the switch means is based on the control signal. An integrated circuit comprising a gate circuit for opening the switch means regardless of the control signal when controlling and designating the second operation mode.