JPH10200335A - Oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an oscillation start voltage and to suppress power consumption in an oscillation holding state by outputting an oscillation stable detecting signal when it is detected that the amplitude value of oscillate signal is a prescribed fixed level, latching this oscillation stable detecting signal and outputting a stop signal. SOLUTION: This circuit is provided with an inverter 3 connected parallelly with an inverter 2 so as to stop the operation in response to the supply of the stop signal Q setting its gain higher than the inverter 2 and an inverter 4 for outputting an oscillation stable detecting signal T when it is detected that the amplitude value of oscillate signal reaches the prescribed level. Further, a latch circuit 5 is provided for latching the oscillation stable detecting signal T and outputting the stop signal Q and an inverted stop signal QB. Then, at the start time, the oscillation is started by the high gain of inverter 3 and when the oscillation is stabilized into oscillation holding state, the inverter is switched to the low gain inverter 2. Therefore, power consumption can be suppressed by the low gain inverter 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an oscillation circuit, and more particularly, to an oscillation circuit using a piezoelectric vibrator such as a crystal vibrator.

[0002]

2. Description of the Related Art In recent years, with an increase in the scale of integrated circuits and an increase in information processing speed, an oscillator circuit with high speed and low power consumption has been increasingly required. In particular, low power consumption is indispensable when operating on batteries, so this type of circuit stops oscillation during standby to reduce the power consumption of the entire circuit, and starts oscillation as soon as possible when using this circuit. In general, the operation state is changed to the operation state. Needless to say, low power consumption is also required during operation.

Generally, in order to shorten the oscillation start time after the power supply of the oscillation circuit is turned on, it is necessary to increase the gain and current capability of the oscillation circuit and increase the energy supplied to the oscillation element such as a crystal oscillator or a ceramic oscillator. Although indispensable, this causes an increase in current consumption, and contradicts low power consumption. In addition, a certain amount of operating current is required for stable operation after the start of oscillation.

As this type of oscillation circuit, a crystal oscillation circuit using a quartz oscillator as a piezoelectric oscillator and a CMOS inverter circuit as an amplifier as an amplifier is called a non-adjustment circuit and is widely known. In addition, a load resistor is inserted into the drain of each of the P-channel type and N-channel type MOS transistors constituting the CMOS inverter circuit, and by appropriately selecting the load resistance value, the oscillation start time can be reduced and the oscillation can be reduced. It is also well known that stabilization and reduction of current consumption are attempted.

First, referring to FIG. 3 which shows a circuit diagram of a conventional first oscillator circuit without the load resistor, the conventional oscillator circuit is connected between an input terminal XI and an output terminal XO and has an oscillator element. , A feedback resistor R1 connected in parallel with the crystal oscillator 1, and an inverter 2 having an input terminal connected to the input terminal XI and an output terminal connected to the output terminal XO.
And

The inverter 2 has a P-channel enhancement MOS transistor P21 having a gate connected to one electrode of the crystal unit 1 via the terminal XI, a source connected to the power supply VDD, and a drain connected to the output terminal XO. Are connected to the gate of the transistor P21, the source is connected to the ground potential (GND), and the drain is connected to the drain of the transistor P21.
And an S-type transistor N21.

In operation, the loop gain including the resistor R1 and the inverter 2 is 0 dB at the phase of 0 °.
Oscillation occurs when the above occurs.

Next, the oscillation circuit described in Japanese Patent Application Laid-Open No. 64-64403 (Document 1) is provided with an N-channel or P-channel depletion type MOS transistor as the load resistor, and has a variable gate resistance to control the internal resistance. By using it as a resistance element, the above-described shortened oscillation start time, stabilized oscillation, and reduced current consumption are achieved by automatic adjustment.

FIG. 3 shows a conventional second oscillation circuit described in Document 1.
Referring to FIG. 4A, which is a circuit diagram using common characters / numerals for common components, the second conventional oscillation circuit has the same crystal oscillation as the first first oscillation circuit. In addition to the inverter 1 and the resistor R1, a CMOS-type inverter 1 which is an amplification circuit including a variable resistance circuit 101 instead of the inverter 2
00 and a voltage generation circuit 102 for controlling an equivalent resistance value of the variable resistance circuit 101.

The inverter 100 includes a transistor P21,
N21 and P-channel depletion MOS type transistors PD1 and PD2 which respectively constitute the variable resistance circuit 101 and are connected in series. The gate of the transistor PD1 is connected to the output of the voltage generation circuit 102, the source is connected to the drain of the transistor P21, and the drain is connected to the other electrode of the crystal unit 1. The gate of the transistor PD2 is connected to the gate of the transistor PD1 and the source is the drain of the transistor PD1. And the drain is connected to the drain of the transistor N21.

Next, FIG. 4A and the voltage generation circuit 10
The operation of the conventional oscillation circuit will be described with reference to FIG. 4B showing the resistance value characteristics of the variable resistance circuit 101 corresponding to the input / output characteristics of FIG. Transistors PD1, with respect to the input voltage O of
Graph R shows the gate voltage VG-drain current characteristic of PD2, and graph R shows the gate voltage VG-source-drain resistance R characteristic of transistors PD1 and PD2, respectively. First, the voltage generation circuit 102 is composed of, for example, a half-wave rectification circuit used for a diode and a smoothing circuit composed of a resistor and a capacitor. The output voltage VG corresponding to the output voltage of this oscillation circuit, that is, the input voltage O of the voltage generation circuit 102 is shown. Is supplied to the gates of the transistors PD1 and PD2 as a gate voltage VG. Each of these transistors PD1 and PD2
It is controlled by a source-drain resistance R corresponding to the gate voltage VG, and this resistance R becomes a drain load resistance of each of the transistors P21 and N21 constituting the inverter 100. When the output voltage of the oscillating circuit increases, the resistance R increases, thereby operating in the direction of suppressing the gain and the current consumption. In addition, when the performance of the transistors P21 and N21 is reduced at the start of oscillation or due to manufacturing variation, the resistance R decreases with the decrease of the oscillation output O, the gain increases, and the oscillation output voltage O and the consumption Automatically adjust to keep the current properly.

As described above, the reason why the variable resistance circuit 101 is formed of a depletion MOS transistor is that the depletion MOS transistor has a finite resistance without turning off even if the gate voltage is lower than the threshold voltage VT. This is because the function of R can maintain the stability of the oscillation operation at the start of oscillation or when the gate voltage becomes close to the threshold value.

[0013]

The above-mentioned conventional first oscillation circuit has a drawback that power consumption is large.

In the conventional second oscillation circuit for low power consumption, the power consumption of the variable resistor circuit cannot be increased in order to reduce the oscillation start voltage. On the other hand, if the resistance value of the variable resistor circuit is large, power consumption can be reduced, but there is a drawback that the oscillation start voltage increases due to a decrease in gain.

An object of the present invention is to provide an oscillation circuit having a low oscillation start voltage and low power consumption during an oscillation operation.

[0016]

An oscillation circuit according to the present invention comprises a piezoelectric vibrator connected between an input terminal and an output terminal, a feedback resistor connected in parallel with the piezoelectric vibrator, and an input terminal connected to the input terminal. The output terminals are connected to the output terminals, respectively.
An oscillation circuit comprising a first inverter circuit having a first gain and a second inverter circuit connected in parallel with the first inverter circuit and having a gain set to a second gain higher than the first gain. A second inverter circuit for stopping the operation, a third inverter for detecting that the oscillation signal amplitude value is at a predetermined constant level and outputting an oscillation stability detection signal, and latching the oscillation stability detection signal, And a latch circuit for outputting a stop signal.

[0017]

FIG. 3 shows an embodiment of the present invention.
Referring to FIG. 1 which is a circuit diagram using common characters / numbers for common components, the oscillator circuit of the present embodiment shown in FIG.
In addition to the inverter 2 and the inverter 2, it is connected in parallel with the inverter 2 so that the gain is set higher than that of the inverter 2 and the stop signal Q
Inverter 3 which stops operation in response to the supply of power, inverter 4 which detects that the oscillation signal amplitude value has reached a predetermined level and outputs oscillation stability detection signal T, and latches oscillation stability detection signal T to stop Signal Q, inverted stop signal Q
And a latch circuit 5 for outputting B.

The inverter 3 has P-channel enhancement MOS (hereinafter referred to as PMOS) transistors P31 and N connected in common with each gate connected to an input terminal XI and connected in common with their drains connected to an output terminal XO.
A channel enhancement MOS (NMOS) transistor N31, a PMOS transistor P32 having a source connected to the power supply VDD and a drain connected to the source of the transistor P31 and receiving a reverse stop signal QB at the gate, and a drain connected to the ground G An NMOS transistor N32 connected to the source of the transistor N31 and receiving the stop signal Q at the gate.

The inverter 4 has a gate connected to the output terminal XO and outputs an oscillation stability detection signal T, and a PMOS transistor P41. The gate is connected to the gate of the transistor P41, the drain is connected to the drain of the transistor P41, and the source is connected to the ground G. NNMOS transistor N41
And a source connected to the power supply VDD and a drain connected to the transistor P4.
And a NMOS transistor N42 having a gate connected to the ground G and a drain connected to the drain of the transistor N41, and a gate connected to the drain of the transistor N41 and receiving the inverted stop signal QB. And

The latch circuit 5 cross-connects the input and output with each other to form a stop signal Q and an inverted stop signal QB, respectively.
Are output from the NOR gates NO1 and NO2.

FIG. 2 shows the input / output characteristics of the inverters 2 and 3 and the stability detection operation after the start of oscillation.
The operation of the present embodiment will be described with reference to (A) and (B). The inverter 2 is set to a lower gain than usual, and the inverter 3 is set to a higher gain than the inverter 2 as described above. The threshold level t1 of the inverter 4 is set lower than the threshold level t2 of the inverters 2 and 3 by the level difference DT.

First, in the initial state, the NOR circuit of the latch circuit 5
The stop signal Q output from the gate NO1 is at H level, NO
The inverted stop signal QB at the output of the R gate NO2 is at the L level, and therefore the transistors P32, N32, P
Reference numeral 42 denotes a conductive state, and transistor N42 denotes a cut-off state. Therefore, inverters 2 and 3 operate in parallel and start oscillating around input signal level threshold value t2. At this time, since the inverter 3 has a higher gain, the oscillating operation is performed by the inverter 3. On the other hand, when the level of the output signal O of the output terminal XO exceeds a predetermined threshold level t1, the output of the inverter 4 rises as shown in a graph A of FIG. In response to the supply of the oscillation stabilization detection signal T, the latch circuit 5 changes the stop signal Q to L level and the inverted stop signal QB to H level. Thereby, the transistor P
32, N32 and P42 are turned off, and the transistor N4
2 changes to the conducting state, and the inverters 3 and 4 stop. Therefore, only the inverter 2 with a low gain maintains the operating state.

That is, when the oscillation rises, the inverter 3
When the oscillation is stabilized and the oscillation is held, the inverter 2 is switched to the low gain inverter 2 to suppress power consumption. The oscillation amplitude in this case is the level difference DT between the threshold levels t1 and t2.

Here, the gain of the inverter 2 is set to
Of the gain of the normal inverter 2 in the oscillation circuit of FIG.
, The power consumption in the oscillation holding state can be halved. Further, the oscillation start voltage is equivalent to the case where the gain of the inverter 3 is set to の of the gain of the normal inverter 2 under the above conditions, but can be further reduced by increasing the gain of the inverter 3. Since the operation of the inverter 3 is stopped in the oscillation holding state, there is no influence on the power consumption.

Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications are possible. For example, it is possible to provide a counter for counting the oscillation stabilization detection signal and to output a stop signal after checking several times to obtain a more stable circuit operation.

[0026]

As described above, the oscillation circuit of the present invention is connected in parallel with the first inverter circuit, sets the gain to be higher than that of the first inverter circuit, and responds to the supply of the stop signal. A second inverter circuit for stopping the operation, a third inverter for detecting that the oscillation signal amplitude value is at a predetermined constant level, and outputting an oscillation stability detection signal;
By providing a latch circuit that latches the oscillation stability detection signal and outputs the stop signal, the oscillation start voltage is reduced and the power consumption in the oscillation holding state is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an oscillation circuit of the present invention.

FIG. 2 is a characteristic diagram showing an input / output characteristic and an oscillation start characteristic of an inverter showing an example of an operation of the oscillation circuit of the present embodiment.

FIG. 3 is a circuit diagram showing an example of a conventional first oscillation circuit.

FIG. 4 is a circuit diagram and a characteristic diagram showing an example of a conventional second oscillation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Crystal oscillator 2-4,100 Inverter 5 Latch circuit R1 Resistance P21, P31, P32, P41, P42, N21, N
31, N32, N41, N42 Transistor NO1, NO2 NOR gate

Claims (3)

[Claims] 1. A piezoelectric vibrator connected between an input terminal and an output terminal, a feedback resistor connected in parallel with the piezoelectric vibrator, an input terminal connected to the input terminal, and an output terminal connected to the output terminal. An oscillation circuit including a first inverter circuit having a first gain, wherein the oscillation circuit is connected in parallel with the first inverter circuit, sets a gain to a second gain higher than the first gain, and supplies a stop signal. A second inverter circuit that stops operating in response, a third inverter that detects that the oscillation signal amplitude value is at a predetermined constant level and outputs an oscillation stability detection signal, and latches the oscillation stability detection signal And a latch circuit for outputting the stop signal. 2. The piezoelectric device according to claim 1, wherein the first inverter circuit has a gate connected to the input terminal, a source connected to one electrode of the piezoelectric vibrator, a source connected to a first power supply, and a drain connected via the input terminal. The first connected to the other electrode of the vibrator, respectively.
And a second conductive type second MOS transistor having a gate connected to the gate of the first transistor, a source connected to a second power supply, and a drain connected to the drain of the first transistor. A third transistor of a first conductivity type, wherein the second inverter circuit has a gate connected in common, connected to the input terminal, a drain connected in common, and connected to the output terminal. MOS
A transistor and a fourth MOS transistor of a second conductivity type, a source connected to the first power supply, a drain connected to the source of the third transistor, and a gate supplied with an inverted stop signal which is an inverted value of the stop signal. And a second conductivity type having a source connected to the second power supply and a drain connected to the source of the fourth MOS transistor, and having a gate supplied with the stop signal. A third MOS transistor of the first conductivity type, wherein the third inverter has a gate connected to the output terminal and outputs the oscillation stability detection signal.
And an eighth MOS transistor of a second conductivity type having a gate connected to the gate of the seventh transistor, a drain connected to the drain of the seventh transistor, and a source connected to the second power supply. The oscillation circuit according to claim 1, wherein: 3. The third inverter has a source connected to the first inverter.
A ninth MOS transistor of a first conductivity type having a drain connected to the source of the seventh transistor and receiving the inversion stop signal at the gate, and a drain connected to the second power source 3. The oscillation circuit according to claim 2, further comprising a second conductivity type tenth MOS transistor connected to the drain of each of the eight transistors and receiving the inverted stop signal at the gate.