JP2626589B2 - Oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillating circuit, and more particularly to an oscillating circuit using an amplifier comprising a piezoelectric vibrator such as a quartz vibrator and a CMOS inverter.

[0002]

2. Description of the Related Art In recent years, with an increase in the scale of integrated circuits and an increase in information processing speed, an oscillator circuit with high speed and low power consumption has been increasingly required. In particular, low power consumption is indispensable when operating on batteries, so this type of circuit stops oscillation during standby to reduce the power consumption of the entire circuit, and starts oscillation as soon as possible when using this circuit. In general, the operation state is changed to the operation state. Needless to say, low power consumption is also required during operation.

In general, in order to shorten the oscillation start time after turning on the power of the oscillation circuit, it is necessary to increase the gain and current capability of the oscillation circuit and to increase the energy supplied to the oscillation element such as a crystal oscillator. This causes an increase in current consumption, which is contrary to low power consumption. In addition, a certain amount of operating current is required for stable operation after the start of oscillation.

As this type of oscillation circuit, a crystal oscillation circuit using a quartz oscillator as a piezoelectric oscillator and a CMOS inverter circuit as an amplifier as an amplifier is called a non-adjustment circuit and is widely known. In addition, a load resistor is inserted into the drain of each of the P-channel type and N-channel type MOS transistors constituting the CMOS inverter circuit, and by appropriately selecting the load resistance value, the oscillation start time can be reduced and the oscillation can be reduced. It is also well known that stabilization and reduction of current consumption are attempted. Further, Japanese Patent Application Laid-Open No. 64-64403 (Document 1)
The oscillation circuit described above includes an N-channel type or P-channel type depletion type MOS transistor as the load resistance and is used as a variable resistance element whose internal resistance is controlled by a gate voltage, thereby shortening the oscillation start time and stabilizing the oscillation. And the reduction of current consumption is achieved by automatic adjustment.

Referring to FIG. 6, which is a circuit diagram of a conventional oscillation circuit described in Document 1, this conventional oscillation circuit includes a crystal unit 1 as an oscillation element and a CMOS as an amplification circuit including a variable resistance circuit 3. It has an inverter circuit 2, a voltage generation circuit 4 for controlling an equivalent resistance value of the variable resistance circuit 3, and a feedback resistor R1.

The gate of the inverter circuit 2 is a quartz oscillator 1
And a N-channel enhancement MOS transistor PE1 having a source connected to the power supply VDD and a P-channel enhancement MOS transistor PE1 having a gate connected to the gate of the transistor PE1 and a source connected to the ground potential (GND), respectively. A transistor NE1;
P-channel depletion MOS type transistors PD31, PD31,
And a PD 32. The gate of the transistor PD31 is connected to the output of the voltage generation circuit 4, the source is connected to the drain of the transistor PE1, the drain is connected to the other electrode of the crystal unit 1, the gate of the transistor PD32 is connected to the gate of the transistor PD31, and the source is the transistor PD3.
The drain of the transistor NE1 is connected to the drain of the transistor NE1.

Next, the operation of the conventional oscillation circuit will be described with reference to FIG. 6 and FIG. 2 showing the resistance value characteristics of the variable resistance circuit 3 corresponding to the input / output characteristics of the voltage generation circuit 4. FIG. C is the VG characteristic of the output voltage (gate voltage of the transistors PD31 and PD32) with respect to the input voltage O of the voltage generation circuit 4, and the graph B is the transistor PD3.
1 shows a gate voltage VG-source-drain resistance value R characteristic of PD32. First, the voltage generation circuit 4 includes, for example, a half-wave rectification circuit used for a diode and a smoothing circuit including a resistor and a capacitor. The output voltage VG corresponding to the output voltage of the oscillation circuit, that is, the input voltage O of the voltage generation circuit 4. Is supplied as the gate voltage VG to the gates of the transistors PD31 and PD32. Each of the transistors PD31 and PD32 is controlled by a source-drain resistance R corresponding to the gate voltage VG.
Are transistors PE1 and NE1 forming inverter 2
Becomes the drain load resistance. When the output voltage of the oscillating circuit increases, the resistance R increases, thereby operating in the direction of suppressing the gain and the current consumption. Further, when the performance of the transistors PE1 and NE1 decreases at the start of oscillation or due to manufacturing variations, etc., the resistance R decreases with the decrease of the oscillation output O, the gain increases, and the oscillation output voltage O and the consumption Automatically adjust to keep the current properly.

As described above, the reason why the variable resistance circuit 3 is constituted by the depletion MOS type transistor is that the depletion MOS type transistor has a finite resistance without cutting off even when the gate voltage is equal to or lower than the threshold voltage VT. This is because the function of R can maintain the stability of the oscillation operation at the start of oscillation or when the gate voltage becomes close to the threshold value.

The layout on the chip of the inverter 2 of the conventional oscillating circuit is shown by reference numerals PE1, PD31 and PD3 in FIG.
7, NE1 and d to f are referred to in a plan view. In the inverter circuit 2 shown in FIG. 7, the depletion MOS transistors PD1 and PD2 are structurally similar to the enhancement MOS transistors PE1 and NE1. Therefore, it is necessary to arrange both of them in separate regions on the chip, which requires an extra layout area. In addition, in the IC manufacturing process, an extra step for forming a depletion MOS transistor is required in addition to a step for forming an enhancement MOS transistor, and it is necessary to form another depletion MOS transistor on the same chip. If not, the above-mentioned steps are increased only for this oscillation circuit, which causes an increase in cost.

[0010]

In the above-mentioned conventional oscillation circuit, a depletion MOS transistor having a different structure and a different manufacturing process from an enhancement MOS transistor constituting a large part of a circuit in a chip is used as a variable resistance circuit. Because of the necessity, the layout area on the chip and the number of manufacturing steps are increased, resulting in a drawback that the cost is increased.

[0011]

Oscillator of the invention According to an aspect of the output amplitude corresponding voltage signal of the piezoelectric vibrator and the piezoelectric vibrator
Variable resistance circuit and source whose resistance value changes in response to supply
A gate to a first power supply and a drain to one end of the piezoelectric vibrator.
A first MOS transistor of a first conductivity type having a source connected to one end of the variable resistor circuit and a source connected to a second power source.
Drain the source to the gate of the first transistor
And a second MOS transistor of a second conductivity type, each of which has a source connected to the other end of the variable resistor circuit .
Connecting the drain to the drain of the second transistor
The drain of the star and the other end of the piezoelectric vibrator, respectively.
The a third MOS transistor of the enhancement type of the first conductivity type for varying the source-drain resistance value in response to said voltage No. signal that will be supplied to the connected gate, source
With the gate and the source of the first transistor
It is constituted by a fourth MOS transistor of each <br/> drain to the drain of said third MOS transistor connected in common enhancement type of the first conductivity type.

[0012]

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which components common to those in FIG. 6 are denoted by common reference characters / numbers. The oscillation circuit of the example includes a crystal oscillator 1 common to the related art, a voltage generation circuit 4,
In addition to the resistor R1, in place of the inverter circuit 2, there is provided an inverter circuit 2A including a variable transistor 3A using a transistor PE1 and a common transistor NE1 and a P-channel enhancement MOS transistor PE31 as a variable resistor.

The variable resistor circuit 3A includes a transistor PE31 having a source connected to the drain of the transistor PE1, a gate connected to the output of the voltage generator 4, and a drain connected to the drain of the transistor NE1, and a source connected to the power supply VDD.
P has a gate connected to the gate of the transistor PE1 and a drain connected to the drain of the transistor PE31.
Channel enhancement MOS transistor PE3
2 is provided.

Next, referring to FIG. 1 and FIG. 2 showing the resistance value characteristics of the variable resistance circuit 3A corresponding to the input / output characteristics of the voltage generation circuit 4 on the same graph as that of the conventional variable resistance circuit 3, FIG. In operation, a graph C in FIG. 2 shows the VG characteristic of the output voltage (gate voltage of the transistor PE31) with respect to the input voltage O of the voltage generating circuit 4, and a graph A shows the gate voltage VG of the transistor PE31 and the resistance R between the source and the drain. The characteristics are shown below. First, since no oscillation occurs when the power is supplied to the oscillation circuit, the input voltage O of the voltage generation circuit 4 is 0, and the output voltage VG becomes the GND potential. The resistance value R of the transistor PE31 changes to a low resistance state in response to the GND potential supplied as the gate voltage VG, and sufficient energy due to the large current of the inverter circuit 2A is supplied to the crystal resonator to start oscillation. As in the conventional case, the resistance value R increases as the oscillation output O increases. Further, the oscillation output O increases,
Transistor PE31 based on power supply voltage VDD at which gate voltage VG of transistor PE31 is the source potential
Exceeds the threshold voltage Vt corresponding to the threshold voltage VT, the enhancement MOS transistor PE31 enters a cutoff state, and the resistance value R becomes infinite. Therefore, the transistor PE1 is also turned off, and does not operate as an inverter circuit as it is. Transistor P
The transistor PE32 connected in parallel with E1 holds a certain amount of current even when the transistors PE1 and PE31 are cut off, and maintains the operation of the inverter circuit 2A.

The inverter circuit 2A of the oscillation circuit according to this embodiment
The layout on the chip shown in FIG.
1, PE32, NE1 and ac are shown in a plan view, and FIG. 3 shows an inverter circuit 2 shown in FIG.
A denotes the transistors PE31 and PE of the variable resistance circuit 2A.
32 is an enhancement MOS type transistor having the same structure as the transistors PE1 and NE1, and can be arranged in the same region. Therefore, there is no factor for increasing the layout area. In addition, since only the process of forming the enhancement MOS transistor is required in the IC manufacturing process, a factor that increases the cost during manufacturing is eliminated.

FIG. 4 shows a second embodiment of the present invention in the same manner as in FIG. 1 with common components being denoted by common reference characters / numerals.
Referring to FIG. 1, the first example of the oscillation circuit of this embodiment shown in FIG.
The difference from this embodiment is that, instead of the inverter circuit 2A,
An N-channel transistor of the inverter circuit includes transistors NE1 and NE2 connected in parallel, and includes an inverter circuit 2B having a variable resistance circuit 3B described below instead of the variable resistance circuit 3A.

The variable resistance circuit 3B includes a transistor NE
N1 and NE2, N-channel enhancement MOS transistors NE31 and NE2, which are variable resistance elements connected in series with each other, and N which is connected in parallel with transistors NE1 and NE2 and maintains current when these transistors NE1 and NE2 are cut off. Channel enhancement MO
And an S-type transistor NE33.

The operation of this embodiment will be described with reference to FIG. 4 and FIG. 5 showing the resistance value characteristics of the variable resistance circuit 3B corresponding to the input / output characteristics of the voltage generation circuit 4. The basic operation of this embodiment is as follows. The third embodiment is the same as the first embodiment except that the characteristic of the gate voltage VG versus the resistance value R becomes reversely curved. Here, assuming that the gate voltage VG-resistance value R characteristics of each of the parallel transistors NE31 and NE32 are graphs B and C, respectively, a graph A which is an arbitrary desired characteristic as a combined characteristic of the variable resistance circuit 3B.
Can be obtained.

[0019]

As described above, in the oscillation circuit according to the present invention, the variable resistance circuit changes the resistance between the source and the drain in response to the supply of the voltage signal corresponding to the output amplitude of the piezoelectric vibrator, and is the same as the load transistor. An extra layout for forming a depletion MOS transistor is provided by including a third enhancement-type MOS transistor of a conductivity type and a fourth enhancement-type MOS transistor of the same conductivity type connected in parallel with the load transistor. This has the effect of eliminating cost increase factors such as an increase in area and steps.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an oscillation circuit according to the present invention.

FIG. 2 is a characteristic diagram illustrating an operation of the oscillation circuit of the present embodiment in comparison with a conventional example.

FIG. 3 is a layout diagram showing a layout on a chip of the oscillation circuit of the present embodiment.

FIG. 4 is a circuit diagram showing a first embodiment of the oscillation circuit of the present invention.

FIG. 5 is a characteristic diagram illustrating an operation of the oscillation circuit according to the present embodiment.

FIG. 6 is a circuit diagram illustrating an example of a conventional oscillation circuit.

FIG. 7 is a layout diagram showing a layout on a chip of a conventional oscillation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Quartz crystal oscillator 2, 2A, 2B Inverter circuit 3, 3A, 3B Variable resistance circuit 4 Voltage generation circuit NE1, NE2, NE31-NE33, PE1, PE3
1, PE32, PD31, PD32 Transistor R1 Resistance

Claims (2)

(57) [Claims] 1. A piezoelectric vibrator and the output amplitude of the piezoelectric vibrator
Variable whose resistance value changes in response to the supply of the corresponding voltage signal
The resistance circuit and the source are connected to the first power supply and the gate is set to the piezoelectric vibration.
The drain is connected to one end of the variable resistor circuit at one end.
Connected first MOS transistor of the first conductivity type ;
A source connected to the second power supply and a gate connected to the first transistor
And a second MOS transistor of a second conductivity type having a drain connected to the gate of the variable resistance circuit and a second MOS transistor connected to the other end of the variable resistance circuit, wherein the variable resistance circuit has a source connected to the first transistor.
The drain of the second transistor is connected to the drain of the second transistor.
The connected to the other end of in and the piezoelectric vibrator of the first enhancement type conductive type conductive varying the source-drain resistance value in response to gate <br/> the voltage No. signal that will be supplied to the bets A third MOS transistor, a source connected to the source of the first transistor, a gate connected to the gate, and a drain connected to the drain of the third MOS transistor.
And an enhancement type fourth MOS transistor of the first conductivity type connected in common to the first and second transistors. (2)Gate and source are connected to the second transformer.
A common connection with the gate and source of the
A fifth MOS transistor of the second conductivity type; The variable resistor circuit connects each drain to the first transistor.
Connected to the drain of each transistor
The gates of the second and fifth MOS transistors LesConnect with Inn
Then, the respective gates are commonly connected to each other to
Receiving supplyFirst and second gate voltage vs. source, respectively
Has drain-to-srain resistance characteristicsThe sixth of the second conductivity type
And seventhTransistorWhen,The drain is connected in common with the drain of the first transistor.
The gate and the source are connected to the gate of the second transistor.
Second conductivity type commonly connected to the gate and the source, respectively
The eighth transistor of Claims comprising:
Item 2. The oscillation circuit according to Item 1.