JP3635519B2 - Oscillator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oscillation circuit using a piezoelectric vibrator such as a crystal vibrator.
[0002]
[Prior art]
An oscillation circuit used as a reference clock generation source for a clock or the like connects a piezoelectric vibrator such as a crystal vibrator between input and output terminals of a CMOS inverter, and connects between an input terminal and an output terminal of the CMOS inverter and a constant potential point. A capacitor is connected, and a feedback resistor is connected between the input and output terminals of the CMOS inverter.
[0003]
FIG. 4 is an electric circuit diagram showing a general configuration of an oscillation circuit using such a crystal resonator. 1 is a crystal resonator, 2 is a CMOS inverter, 3 and 4 are capacitors, and 5a is a feedback resistor. The CMOS transistor 6 is an N-channel MOS transistor for stopping oscillation.
[0004]
Normally, a feedback resistor with a large resistance value of several MΩ is used, but since there is no problem in oscillation even if the resistance value varies widely or the temperature change of the resistance value is large (about 50%), the feedback resistor A CMOS transistor 5a composed of a P-channel MOS transistor and an N-channel MOS transistor has been used as a high resistor.
[0005]
In the oscillation circuit configured as described above, when the oscillation stop signal S1 is set to the H level, the CMOS transistor 5a as the feedback resistor is turned off and the N-channel MOS transistor 6 is turned on, so that the input terminal of the CMOS inverter 2 is fixed. Oscillation is stopped by pulling down to the ground potential which is a potential point.
[0006]
On the other hand, it is known that an overtone crystal oscillation circuit can be configured by reducing the resistance value of the feedback resistor. The resistance value is determined according to the order to be oscillated (third-order wave, fifth-order wave, etc.), and is, for example, about 3 to 10 KΩ depending on the conditions of the oscillation circuit.
[0007]
FIG. 5 is an electric circuit diagram showing the configuration of such an overtone crystal oscillation circuit. 5b is a thin film resistor as a feedback resistor, 7 is a DC blocking capacitor, and 8 is a high resistance MOS for setting a DC bias. It is a transistor. Note that elements corresponding to those in FIG. 4 are given the same reference numerals and description thereof is omitted.
[0008]
When the overtone crystal oscillation circuit is configured by reducing the resistance value of the feedback resistor, the cut-off frequency Fc shifts when the resistance value of the feedback resistor 5b changes. For example, in the tertiary overtone oscillation circuit, fundamental oscillation or Predetermined overtone oscillation cannot be stably performed, for example, the oscillation condition changes to fifth-order overtone oscillation. Therefore, as the feedback resistor, a high-precision thin film resistor with little variation or change in resistance value is used instead of a MOS transistor having large variation in resistance value or temperature change in resistance value.
[0009]
Further, in order to prevent an increase in power consumption when oscillation is stopped (when the N-channel MOS transistor 6 is turned on) as a feedback resistor is lowered and a resistor having no switching function is used, a direct current is prevented. A blocking circuit 7 is connected in series to a thin film resistor 5b as a feedback resistor to form a feedback circuit, and in parallel therewith, a MOS transistor 8 having a high resistance (several hundreds KΩ to several MΩ) is provided. A DC bias setting circuit is formed.
[0010]
In this oscillation circuit, when the oscillation stop signal S1 is at L level, the N-channel MOS transistor 6 is turned off and the DC bias setting MOS transistor 8 is turned on to oscillate at an overtone frequency of a predetermined order. When the H level is set, the DC bias setting MOS transistor 8 is turned off and the N-channel MOS transistor 6 is turned on, whereby the input terminal of the CMOS inverter 2 is pulled down to the ground potential which is a constant potential point and oscillation stops. .
[0011]
[Problems to be solved by the invention]
In the conventional oscillation circuit described above, the oscillation stop MOS transistor 6 is connected to the input terminal of the CMOS inverter 2, so that the oscillation stop MOS transistor 6 is oscillated, that is, when the oscillation stop MOS transistor 6 is off. The capacitance component of is directly connected to the input circuit and added to the input capacitance. Since the capacitance component of the added MOS transistor 6 varies depending on the power supply voltage and varies depending on the manufacturing process, it is difficult to obtain an oscillation circuit in which the total input capacitance of the oscillation circuit is not constant and the oscillation frequency is stable. Met.
[0012]
In particular, in the overtone oscillation circuit of FIG. 5, a DC blocking capacitor 7 for preventing an increase in power consumption at the time of stop is provided in the feedback circuit, and a DC bias setting MOS transistor 8 is further provided. Therefore, there is a problem that a large area is required to configure the oscillation circuit, and circuit connection is complicated.
[0013]
Accordingly, an object of the present invention is to obtain an oscillation circuit in which the input capacitance is constant, a DC component blocking capacitor is unnecessary, the required area is small, and the oscillation frequency is stable.
[0014]
[Means for Solving the Problems]
According to another aspect of the present invention, there is provided an oscillation circuit comprising: a CMOS inverter; a piezoelectric vibrator connected between input / output terminals of the CMOS inverter; and a first inverter connected between an input terminal of the CMOS inverter and a first constant potential source. A capacitor, a second capacitor connected between the output terminal of the CMOS inverter and the first constant potential source, a feedback resistor having one end connected to the input terminal of the CMOS inverter, and the other end of the feedback resistor. A switch for switching connection to either the second constant potential source or the output terminal of the CMOS inverter according to an input signal, and the feedback resistor is shared as a pull-down resistor or a pull-up resistor of the input terminal of the CMOS inverter. It is characterized by.
[0015]
According to this configuration, an unstable capacitor component due to the oscillation stopping MOS transistor is not added to the input terminal of the CMOS inverter, the setting of the constants of the oscillation circuit is simplified, and a stable frequency is oscillated. Can do. In addition, a DC blocking capacitor and a MOS transistor having a high resistance value for setting a DC bias, which are conventionally required when oscillating an overtone frequency, are not required, and the oscillation circuit can be configured with a small area. Connection is also easy.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Before describing an embodiment of the present invention, first, the principle of the present invention will be described with reference to FIG. 1A is an overall circuit diagram of the oscillation circuit, FIG. 1B is an oscillation stop state diagram, and FIG. 1C is an oscillation state diagram. In these figures, 1 is a crystal resonator, 2 is a CMOS inverter, 3 and 4 are capacitors, 5c is a feedback resistor, and 9 is a change-over switch for switching the switching contact c from the b-contact to the a-contact by the oscillation stop signal S1. .
[0018]
This oscillation circuit can be configured as a fundamental frequency oscillation circuit or an overtone oscillation circuit, but in the case of a fundamental frequency oscillation circuit, the resistance value of the feedback resistor 5c is set high (for example, about several MΩ), and the overtone In the case of an oscillation circuit, the resistance value of the feedback resistor 5c is set low (for example, about 3 to 10 KΩ).
[0019]
A crystal resonator 1 is connected in parallel between the input / output terminals of the CMOS inverter 2, and capacitors 3 and 4 are connected between the input / output terminal and the ground, respectively. The switching contact c of the changeover switch 9 is connected to the input terminal of the CMOS inverter 2 via the feedback resistor 5c, the contact b of the changeover switch 9 is the output terminal of the CMOS inverter 2, and the contact a of the changeover switch 9 is the constant potential point VSS. Connected to.
[0020]
With this configuration, when the oscillation stop signal S1 is at the L level, the switching contact c of the changeover switch 9 is switched to the a contact side, and the feedback resistor 5c is connected between the input / output terminals of the CMOS inverter 2. The oscillation circuit at this time has a circuit configuration shown in FIG. 1C, and a predetermined DC bias voltage is applied to the input terminal of the CMOS inverter 2, and the frequency of the order according to the value of the feedback resistor 5c (basic frequency or Oscillates at a predetermined overtone frequency).
[0021]
When the oscillation stop signal S1 is at the H level, the switching contact c of the changeover switch 9 is switched to the b contact side, and the feedback resistor 5c is connected to the constant potential point VSS. The oscillation circuit at this time has the circuit configuration shown in FIG. 1B, and the feedback resistor 5c is disconnected from the input / output terminals of the CMOS inverter 2, and the input terminal of the CMOS inverter 2 is connected to a constant potential via the feedback resistor 5c. It is fixed at VSS and stops oscillation.
[0022]
When the oscillation circuit stops oscillating, the input terminal of the CMOS inverter 2 is connected to the constant potential point VSS via the feedback resistor 5c, so that the feedback resistor 5c is used to set the input terminal potential of the CMOS inverter to a fixed potential. It can be shared as a pull-down resistor or a pull-up resistor, and a dedicated pull-down resistor or pull-up resistor can be omitted.
[0023]
According to this oscillation circuit, since the unstable capacitor component due to the oscillation stopping MOS transistor is not added to the input terminal of the CMOS inverter 2 as in the prior art, the setting of the constants of the oscillation circuit is simplified. It is possible to oscillate stably at the frequency of the specified order. In addition, a DC blocking capacitor and a MOS transistor having a high resistance value for setting a DC bias, which are conventionally required when oscillating an overtone frequency, are not required, and the oscillation circuit can be configured with a small area. Connection is also easy.
[0024]
FIG. 2 is a configuration diagram of an oscillation circuit according to an embodiment of the present invention that embodies the principle diagram of the oscillation circuit described in FIG. 1, and the same components as those in FIG. 2 differs from FIG. 1 in that the changeover switch 9 is specifically composed of a MOS transistor.
[0025]
That is, the changeover switch 9 includes an N-channel MOS transistor 9c connected between the other end of the feedback resistor 5c whose one end is connected to the input terminal of the CMOS inverter 2 and the fixed constant potential point VSS, and the feedback resistor 5c. A CMOS transistor 9a composed of a parallel circuit of a P-channel MOS transistor and an N-channel MOS transistor connected between the other end side and the output terminal of the CMOS inverter 2, and an inverter 9b connected to one input terminal of the CMOS transistor 9a And an input line of the oscillation stop signal S1 connected to the other of the MOS transistor 9c and the CMOS transistor 9a and each input terminal of the inverter 9b.
[0026]
The MOS transistor 9a has a CMOS configuration in which a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel in order to improve the function as a switch. Any one of the N-channel MOS transistors can be used.
[0027]
In the circuit configuration of FIG. 2, when the oscillation stop signal S1 is set to the L level, the N-channel MOS transistor 9c is turned off by the oscillation stop signal S1, while the MOS transistor 9a is turned on by the oscillation stop signal S1 and its inverted signal. Then, the feedback resistor 5c is connected between the input / output terminals of the CMOS inverter 2 to form a feedback circuit, and a predetermined DC bias is applied to the input terminal of the CMOS inverter 2, and the oscillation circuit has a frequency of a predetermined order. Stable oscillation is performed at (fundamental frequency or overtone frequency).
[0028]
Conversely, when the oscillation stop signal S1 is set to the H level, the MOS transistor 9a is turned off by the oscillation stop signal S1 and its inverted signal to open the feedback circuit, while the N-channel MOS transistor 9C is turned on by the oscillation stop signal S1. Then, the input terminal of the CMOS inverter 2 becomes the fixed potential VSS, and the oscillation of the oscillation circuit stops.
[0029]
The N-channel MOS transistor 9c and the MOS transistor 9a connected in series with the feedback resistor 5c in this oscillation circuit have a lower resistance than the feedback resistor 5c, and the area of these MOS transistors can be reduced. The resistance value of the MOS transistor 9a varies or fluctuates up to about 50%, and the resistance value of the feedback resistor 5c (about several MΩ for the fundamental frequency oscillation circuit, about 3 to 10 KΩ for the overtone oscillation circuit) ), The variation or fluctuation of the total resistance value of the feedback circuit is small, and this does not cause a circuit problem as an oscillation condition at a predetermined order.
[0030]
The N channel MOS transistor 9c is turned off at the time of oscillation, and the capacitance component of the N channel MOS transistor 9c is connected to the input circuit of the CMOS inverter 2, but is connected via the feedback resistor 5c. Therefore, the influence of the magnitude and variation of the capacitance component of the N-channel MOS transistor 9c on the total input capacitance is extremely small and can be substantially ignored.
[0031]
Therefore, as in the basic oscillation circuit of FIG. 1, the setting of the various numbers of the oscillation circuit is simplified and the oscillation can be performed at a stable frequency. Note that the capacitance component of the N-channel MOS transistor 9c is also connected to the output circuit of the CMOS inverter 2, but in this case as well, it is connected via the resistance of the MOS transistor 9a. Similarly, the effect is small and practically not a problem.
[0032]
In addition, a DC blocking capacitor and a MOS transistor with a high resistance value for DC bias setting, which were conventionally required when oscillating an overtone frequency, are not required, and the oscillation circuit can be configured with a small area and circuit connection. Can also be done easily.
[0033]
In the oscillation circuit of FIG. 2, the changeover switch 9 is formed of a MOS transistor. However, the changeover switch 9 is not limited to a MOS transistor, and a field effect transistor FET that functions as a voltage-controlled bidirectional switch in the same manner as a MOS transistor. For example, it can be composed of a junction field effect transistor JFET or the like.
[0034]
As described above, the oscillation circuit in which the changeover switch 9 is configured by the field effect transistor FET is applied with the oscillation stop signal S1 to the gate of the field effect transistor FET, similarly to the oscillation circuit configured by the MOS transistor. Depending on the H level or L level, the oscillation state or the oscillation stop state is entered.
[0035]
The oscillation circuit in which the changeover switch 9 is configured by a field effect transistor FET has the same effect as in the oscillation circuit in which the changeover switch 9 of FIG. 2 is configured by a MOS transistor.
[0036]
FIG. 3 shows an integrated oscillation circuit according to another embodiment of the present invention in which the oscillation circuit of FIG. 2 is integrated on a semiconductor substrate S such as a silicon substrate. FIG. 6A shows a case where the fixed potential of the input terminal of the CMOS inverter 2 is set to the ground potential when oscillation is stopped, and the MOS transistor 9c for that purpose is an N channel, and the circuit is the same as the oscillation circuit of FIG. . FIG. 5B shows the case where the fixed potential of the input terminal of the CMOS inverter 2 is set to the power supply potential VDD when oscillation is stopped. The MOS transistor 9c for that purpose is the P channel, and the oscillation stop signal S1 has the H / L level and oscillation. The rest is the same as (a) except that the state / stop state relationship is reversed.
[0037]
In FIG. 8A, the oscillation stop signal S1 is oscillated at the L level and stopped at the H level, and in FIG. 5B, the oscillation stop signal S1 is oscillated at the H level and stopped at the L level. Become.
[0038]
When configuring an integrated oscillation circuit, the crystal resonator 1 is externally attached, and other components, that is, a CMOS inverter 2, capacitors 3 and 4, a feedback resistor 5c, a MOS transistor 9a, an inverter 9b, and a MOS transistor 9c are All are integrated on a semiconductor substrate. The feedback resistor 5 is a thin film resistor and is formed with high accuracy with a resistance value corresponding to the oscillation frequency.
[0039]
According to this integrated oscillation circuit, various effects similar to those in the specific oscillation circuit shown in FIG. 2 described above are obtained, and a surge voltage is externally applied to an external terminal for a crystal resonator attached to a semiconductor substrate. Is applied, the feedback resistor 5c and the CMOS transistor 9c function as protective resistors for the MOS transistor 9c, and the surge voltage is attenuated. Therefore, unlike the conventional oscillation circuit, no surge voltage is directly applied to the pull-down or pull-up MOS transistor 9c, and there is no need to increase the breakdown voltage. Therefore, the size of the MOS transistor 9c can be reduced. it can.
[0040]
【The invention's effect】
According to the configuration of the first aspect of the present invention, an unstable capacitor component due to the oscillation stopping MOS is not added to the input terminal of the CMOS inverter, and the setting of the constants of the oscillation circuit is simplified and stable. Can oscillate various frequencies. In addition, a DC blocking capacitor and a MOS transistor switch having a high resistance value for setting a DC bias, which are conventionally required when oscillating an overtone frequency, are not required, and an oscillation circuit can be configured with a small area. Easy circuit connection.
[0041]
In addition, when oscillation stops, the input terminal of the CMOS inverter is connected to a constant potential point via a feedback resistor, so the feedback resistor can be shared as a pull-down resistor or pull-up resistor for setting the input terminal potential of the CMOS inverter, and a dedicated pull-down resistor A resistor or a pull-up resistor can be omitted.
[Brief description of the drawings]
FIG. 1 is an oscillation circuit diagram showing the principle of the present invention. FIG. 1 (a) is an overall circuit diagram, FIG. 1 (b) is an oscillation stop state diagram, and FIG. 1 (c) is an oscillation state diagram. FIG.
FIG. 2 is a diagram illustrating an oscillation circuit according to an embodiment of the present invention.
FIGS. 3A and 3B are diagrams showing an integrated oscillator circuit according to another embodiment of the present invention, in which FIGS. 3A and 3B show a fixed potential at the input terminal of the CMOS inverter 2 when oscillation is stopped, respectively. FIG. 6 is a diagram illustrating a ground potential and a power supply potential VDD.
FIG. 4 is a diagram showing a conventional general oscillation circuit.
FIG. 5 is a diagram illustrating a conventional overtone oscillation circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Crystal oscillator 2 CMOS inverter 3 Capacitor 4 Capacitor 5a CMOS transistor 5b, 5c as feedback resistance Feedback resistor 6 Oscillation stopping MOS transistor 7 DC blocking capacitor 8 DC bias setting MOS transistor 9 Changeover switch 9a MOS transistor 9b Inverter 9c MOS transistor

Claims (1)

A CMOS inverter; a piezoelectric vibrator connected between input and output terminals of the CMOS inverter; a first capacitor connected between the input terminal of the CMOS inverter and a first constant potential source; and an output of the CMOS inverter A second capacitor connected between the terminal and the first constant potential source, a feedback resistor having one end connected to the input terminal of the CMOS inverter, and the other end of the feedback resistor connected to the second constant according to the input signal A switch for switching connection to either the potential source or the output terminal of the CMOS inverter,
An oscillation circuit characterized in that the feedback resistor is shared as a pull-down resistor or a pull-up resistor of an input terminal of the CMOS inverter .

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