JP3155977B2 - Oscillation integrated circuit and oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation integrated circuit and an oscillation circuit.

[0002]

2. Description of the Related Art At present, in an oscillation circuit used as a reference clock generation source in a clock or the like, a piezoelectric vibrator such as a crystal vibrator is connected between input and output terminals of a CMOS inverter, and further, between input and output terminals of the CMOS inverter. A feedback resistor is connected. Generally, a feedback resistor having a large value of about several MΩ is used. However, by setting the resistance value to a small value of about several KΩ, overtone oscillation can be performed. In
There is one disclosed in Japanese Utility Model Laid-Open No. 3-22417. As shown in FIG. 6, a CMOS inverter 61, a feedback resistor 62 having a resistance of about several MΩ connected between input and output terminals of the CMOS inverter 61, and a CM
A capacitor 63 as a load capacitance connected to each of the input terminal in and the output terminal out of the OS inverter 61
And a series circuit 6 in which a capacitor 64 and a feedback resistor 65 having a resistance value of about several KΩ are connected in series.
6 is an input terminal in and an output terminal ou of the CMOS inverter.
, a MOS transistor 67 is provided between the input terminal in of the CMOS inverter 61 and the ground, and the crystal oscillator 69 is connected to the CMOS inverter 6.
1 is externally connected between the input and output terminals. This is the selection terminal S
6, the MOS transistor 67 is selectively turned on and off, and the MOS transistor 67 is turned off to cut off the connection between the input terminal in of the CMOS inverter 61 and the ground. 62 and a direct current
To make AC feedback and generate overtone oscillation, MOS
By turning on the transistor 67, the input terminal i
n is connected between n and ground to stop the oscillation by keeping the potential of the input terminal at a predetermined value.

[0003]

SUMMARY OF THE INVENTION In such a case,
Turn on MOS transistor 67 to stop oscillation
When the input terminal in of the OS inverter 61 is grounded, C
From the output terminal out of the MOS inverter 61 to the feedback resistor 6
The current leaks to the ground side via 2 and the current is wasted. For this reason, the resistance value of the feedback resistor 62 is increased to reduce the current leakage at the time of stopping the oscillation.
However, the feedback resistor 62 is connected to the CMOS inverter 6
Since the input / output potential of 1 is also set as an operation point of the CMOS inverter (for example, a value of 電源 of the power supply potential), it cannot be set to an unnecessarily high value. For this reason, when the oscillation is stopped, the leakage of the current via the feedback resistor 62 is still unavoidable, which is insufficient for suppressing unnecessary current consumption.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an oscillation integrated circuit and an oscillation circuit in which unnecessary current consumption when oscillation is stopped is suppressed.

[0005]

SUMMARY OF THE INVENTION A CMOS inverter;
A feedback resistor connected in parallel with the CMOS inverter, connecting a load capacitance to each of the input terminal and the output terminal of the CMOS inverter,
In an oscillation integrated circuit in which a piezoelectric vibrator is externally connected between the input and output terminals of the OS inverter, the feedback resistor is constituted by a MOS transistor, and a second feedback resistor having a lower resistance value than the MOS transistor and a capacitive element are connected. A series circuit connected in series is connected in parallel to the MOS transistor, and a control circuit for holding an input terminal or an output terminal of the CMOS inverter at a desired potential by an oscillation stop signal is provided. MOS above
Turn off the transistor.

A CMOS inverter and a feedback resistor connected in parallel to the CMOS inverter;
In an oscillation integrated circuit in which a load capacitor is connected to each of an input terminal and an output terminal of a MOS inverter and a piezoelectric vibrator is externally connected between the input and output terminals of the CMOS inverter, the feedback resistor is constituted by a MOS transistor. A series circuit comprising the MOS transistor and a second feedback resistor having a lower resistance value than the MOS transistor connected in series, connected in parallel to the CMOS inverter, and a capacitor connected in parallel to the MOS transistor; A control circuit is provided for holding the input terminal or the output terminal of the CMOS inverter at a desired potential by an oscillation stop signal, and the MOS transistor is turned off by the oscillation stop signal.

A CMOS inverter, a piezoelectric vibrator connected between the input and output of the CMOS inverter, and the CM
A feedback resistor connected in parallel with the OS inverter;
In an oscillation circuit including a load capacitor connected to each of an input terminal and an output terminal of a MOS inverter, the feedback resistor is constituted by a MOS transistor, and a second feedback resistor having a lower resistance value than the MOS transistor, a capacitor, and Are connected in series to the above MOS
A control circuit is connected in parallel with the transistor, and a control circuit for holding an input terminal or an output terminal of the CMOS inverter at a desired potential by an oscillation stop signal is provided, and the MOS transistor is turned off by the oscillation stop signal.

[0008] A CMOS inverter, a piezoelectric vibrator connected between the input and output of the CMOS inverter, and the CM
A feedback resistor connected in parallel with the OS inverter;
In an oscillation circuit comprising a load capacitor connected to each of an input terminal and an output terminal of a MOS inverter, the feedback resistor is constituted by a MOS transistor, and the second feedback resistor having a lower resistance than the MOS transistor and the CMOS transistor. Are connected in parallel to the CMOS inverter, a capacitor is connected in parallel to the MOS transistor, and an input terminal or an output terminal of the CMOS inverter is set to a desired potential by an oscillation stop signal. Is provided, and the MOS transistor is turned off by the oscillation stop signal. Thus, the above object is achieved.

[0009]

Next, an embodiment of the present invention will be described. FIG. 1 is an electric circuit diagram showing the configuration of the present embodiment. In FIG. 1, reference numeral 1 denotes a CMOS inverter, and a capacitor 2 as a load capacitance is connected to each of an input terminal IN and an output terminal OUT of the CMOS inverter 1. Is done. As the capacitor 2, an external capacitor or a gate capacitor may be used. However, a capacitor having a smaller resistance component is preferable. For example, a capacitor via a dielectric as disclosed in JP-A-5-191145 may be used. It is preferable to use a capacitor including a pair of conductive layers facing each other. As shown in FIG. 2, a field insulating layer 22 is formed on a silicon substrate 21 and a metal layer 2 serving as a lower electrode of a capacitor is formed thereon.
3, a dielectric layer 24 is formed thereon, and a second metal layer 25 serving as an upper electrode of the capacitor is formed thereon. In FIG. 2, reference numeral 26 denotes an interlayer insulating layer, and reference numeral 27 denotes an extraction electrode of a lower electrode.

Referring again to FIG. 1, reference numeral 3 denotes a crystal oscillator serving as a piezoelectric oscillator, which is externally connected between the input / output terminal OUT of the CMOS inverter 1.

4 is a P-channel type MO as a feedback resistor.
It is an S transistor, and its drain and source are C
The MOS inverter 1 is connected to the input terminal IN and the output terminal OUT, and the gate is connected to the selection terminal S1. When the selection terminal S1 receives an oscillation stop signal, it is turned off. Also,
The on-resistance value is about 1 to 5 MΩ, and the input / output potential of the CMOS inverter 1 is set to a value that is set to the operating point of the CMOS inverter 1 (１ ／ of the power supply potential).

Reference numeral 5 denotes a capacitor as a capacitance element.
A gate capacitance may be used, or a configuration similar to the above-described load capacitance may be used. Reference numeral 6 denotes a second feedback resistor, which has a resistance lower than the ON resistance of the MOS transistor 4, for example, 0.
Set to about 5 to 10 KΩ. The capacitor 5 and the second feedback resistor 6 are connected in series to form a series circuit 7, and the series circuit 7 is connected to the MOS transistor 4 in parallel.

Reference numeral 8 denotes an N-channel MOS transistor whose drain and source are connected to the input terminal IN and the ground GND of the CMOS inverter 1, respectively, and the gate is connected to the selection terminal S1. It is turned on when it receives. This MOS transistor 8
And the selection terminal S1 constitute a control circuit for holding the input terminal or the output terminal of the CMOS inverter at a desired potential when oscillation stops. Next, the operation of this example will be described. First, when the selection terminal S1 is set to “L”, the MOS transistor 4 is turned on and the MOS transistor 8 is turned off. When the MOS transistor 4 is turned on, the input terminal IN and the output terminal O of the CMOS inverter 1 are turned on.
The UTs conduct, and are biased by the ON resistance of the MOS transistor 4. At the same time, when the MOS transistor 8 is turned off, the input terminal IN of the CMOS inverter 1 and the ground are cut off, and oscillation starts. Since the capacitor 5 is connected to the second feedback resistor, no current flows in a DC manner. However, as the frequency of oscillation increases, the dominance of the resistance value of the second feedback resistor 6 in oscillation increases. Since the value is set to about 0.5 to 10 KΩ, overtone oscillation is performed.

Next, when it is desired to stop the oscillation, when the selection terminal S1 is set to "H", the MOS transistor 4 is turned off and the MOS transistor 8 is turned on. When the MOS transistor 4 is turned off, the connection between the input terminal IN and the output terminal OUT of the CMOS inverter 1 is cut off. At the same time, when the MOS transistor 8 is turned on, the CM
Oscillation is stopped when the input terminal IN of the OS inverter 1 is connected to the ground and the input terminal IN of the inverter 1 is held at "L". Here, the DC connection of the series circuit 7 is cut off by the capacitor 5, and when the MOS transistor 4 is turned off, the connection between the input terminal IN and the output terminal OUT of the CMOS inverter 1 is reliably cut off. As a result, no current flows from the output terminal OUT of the CMOS inverter 1 to the input terminal IN.

In the conventional device, the CMO is used to stop oscillation.
When the input terminal IN of the S inverter is held at “L”, C
Although the current flows from the output terminal OUT of the MOS inverter to the input terminal IN and wastes current, as described above, in this example, the output terminal of the CMOS inverter 1 is turned off by turning off the MOS transistor 4. The current flowing from OUT to the input terminal IN is surely cut off, and it is possible to suppress unnecessary current consumption when the oscillation is stopped.

Further, the present invention is not limited to the above embodiment, but can be modified as shown in FIG. This is because a P-channel type MOS transistor 31 as a feedback resistor and a second feedback resistor 32 having a lower resistance value than the ON resistance value of the MOS transistor 31 are connected in series to a CMOS inverter. 34, an input terminal IN3 of the CMOS inverter 34 is connected to the input terminal IN3 of the CMOS inverter 34.
A channel type MOS transistor 36 is connected.
Also, the MOS transistor 31, the MOS transistor 3
The selection terminal S3 as a control circuit is connected to the gate of No. 6. Reference numerals 37 and 38 denote a quartz oscillator as a piezoelectric oscillator and a capacitor as a load capacitance, respectively.
Also in this case, as in the above-described embodiment, the oscillation operation and the oscillation stop operation are performed according to the oscillation stop signal from the selection terminal S3, and the same operation and effect can be obtained.

In each of the above embodiments, the CMOS
The piezoelectric vibrator and the load capacitance may not be directly connected to the output terminal of the inverter, but may be connected via a limiting resistor (for example, about 6 KΩ). By doing so, the load on the CMOS inverter can be reduced, and low power consumption can be achieved. For example, the circuit configuration of the example of FIG. 1 can be changed as shown in FIG.
In the figure, the same reference numerals as those shown in FIG.
A limiting resistor RD is connected to the UT, and the crystal resonator 3 and the capacitor 2 are connected via the limiting resistor RD.

In each of the above-described embodiments, the MOS transistor provided between the input terminal of the CMOS inverter and the ground is turned on by the oscillation stop signal “H”, and the CMOS transistor is turned on.
Although the input terminal of the S inverter is grounded to stop the oscillation by holding the input terminal at “L”, the present invention is not limited to this, and the input terminal of the CMOS inverter and the power supply VDD may be connected to each other. May be provided with a P-channel type MOS transistor, turned on by an oscillation stop signal, connecting the input terminal of the CMOS inverter to a power supply, and holding the input terminal at "H" to stop oscillation. Good. For example, in the circuit configuration of the example of FIG.
Can be changed as shown in FIG. In the figure, the same reference numerals as those shown in FIG. 1 denote the same components, and instead of the P-channel type MOS transistor 4, N
A channel type MOS transistor 51 is provided, and a P channel type MOS transistor 52 is provided instead of the N channel type MOS transistor 8. The gates of the MOS transistors 51 and 52 are connected to the selection terminal S5, and when the oscillation stop signal “L” is output from the selection terminal S1, contrary to the above-described embodiment, the oscillation is stopped.
When the oscillation stop signal “H” is output, oscillation starts.
In this case, the same operation and effect as those of the above embodiments can be obtained.

In each of the above embodiments, a quartz oscillator is used as the piezoelectric oscillator. However, the present invention is not limited to this. For example, a ceramic oscillator such as a PZT type or a PbTiO ₃ type may be used. Good.

Further, in each of the above embodiments, the MO receiving the oscillation stop signal at the gate is provided to the input terminal side of the CMOS inverter.
Although an S transistor is provided as a control circuit, this is turned on by an oscillation stop signal, and the oscillation is stopped by holding the input terminal of the CMOS inverter at a desired potential.
However, the present invention is not limited to this. An MOS transistor is provided on the output terminal side of the CMOS inverter for receiving an oscillation stop signal at its gate, and is turned on by the oscillation stop signal to hold the output terminal of the CMOS inverter at a desired potential and oscillate. May be stopped.

[0021]

According to the present invention, it is possible to provide an oscillation integrated circuit and an oscillation circuit in which unnecessary current consumption when oscillation is stopped is suppressed.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is a sectional view showing a configuration of a main part in FIG. 1;

FIG. 3 is an electric circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is an electric circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is an electric circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 6 is an electric circuit diagram showing a configuration of a conventional oscillation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CMOS inverter 2 Capacitor (load capacity) 3 Crystal oscillator (piezoelectric oscillator) 4 MOS transistor 5 Capacitor (capacitance element) 6 Feedback resistor (second feedback resistor) 7 Series circuit 8 MOS transistor (control circuit) S1 selection terminal (Control Circuit) 31 MOS Transistor 32 Feedback Resistance (Second Feedback Resistance) 33 Series Circuit 34 CMOS Inverter 35 Capacitor (Capacitance Element) 36 MOS Transistor (Control Circuit) S3 Selection Terminal (Control Circuit) 37 Crystal Vibrator (Piezoelectric Vibration) 38) Capacitor (load capacity) 51 MOS transistor 52 MOS transistor (control circuit) S5 selection terminal (control circuit)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03B 5/30-5/42

Claims (4)

(57) [Claims] 1. An oscillation integrated circuit comprising a CMOS inverter and a feedback resistor connected in parallel to the CMOS inverter, wherein a piezoelectric vibrator is externally connected between input and output terminals of the CMOS inverter. The feedback resistor is constituted by a MOS transistor, and a series circuit including a second feedback resistor having a lower resistance value than the MOS transistor and a capacitor is connected in series to the MO.
A control circuit connected in parallel to the S transistor to hold an input terminal or an output terminal of the CMOS inverter at a desired potential by an oscillation stop signal; and turning off the MOS transistor by the oscillation stop signal. Oscillation integrated circuit. 2. An oscillation integrated circuit comprising a CMOS inverter and a feedback resistor connected in parallel to the CMOS inverter, wherein a piezoelectric vibrator is externally connected between input and output terminals of the CMOS inverter. The feedback resistor is constituted by a MOS transistor, a series circuit formed by connecting this MOS transistor and a second feedback resistor having a lower resistance value than the MOS transistor in series is connected in parallel to the CMOS inverter, and the capacitance element is connected to the CMOS inverter. A control circuit connected in parallel to the MOS transistor to hold an input terminal or an output terminal of the CMOS inverter at a desired potential by an oscillation stop signal; and turning off the MOS transistor by the oscillation stop signal. Oscillation integrated circuit. 3. A CMOS inverter, a piezoelectric vibrator connected between the input and output of the CMOS inverter, and the C
In an oscillation circuit including a feedback resistor connected in parallel to a MOS inverter and load capacitors connected to input terminals and output terminals of the CMOS inverter, the feedback resistor is configured by a MOS transistor. A series circuit formed by connecting a second feedback resistor having a low resistance value and a capacitance element in series is connected to the MO.
A control circuit connected in parallel to the S transistor to hold an input terminal or an output terminal of the CMOS inverter at a desired potential by an oscillation stop signal; and turning off the MOS transistor by the oscillation stop signal. Oscillation circuit. 4. A CMOS inverter, a piezoelectric vibrator connected between input and output of the CMOS inverter,
In an oscillation circuit including a feedback resistor connected in parallel to a MOS inverter and a load capacitor connected to each of an input terminal and an output terminal of the CMOS inverter, the feedback resistor is configured by a MOS transistor. A series circuit in which a second feedback resistor having a lower resistance value than the MOS transistor is connected in series is connected in parallel to the CMOS inverter, a capacitor is connected in parallel to the MOS transistor, and an oscillation stop signal is used. An oscillation circuit, comprising: a control circuit for holding an input terminal or an output terminal of the CMOS inverter at a desired potential; and turning off the MOS transistor by the oscillation stop signal.