JP2001102867A - Oscillation control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation control circuit capable of miniaturizing/ lightening electronic equipment or the like and reducing the cost by omitting the large capacitance capacitor and reducing the chip area. SOLUTION: Concerning an oscillation control circuit 10 capable of controlling the oscillation frequency of an oscillation circuit provided with a vibrator 1 connected to a first or second connecting terminal X1 or X2, this circuit is provided with an inverter 13 to be functioned as the amplifier of the said oscillation circuit and first and second load capacitors 16a and 16b connected to the respective said first and second connecting terminals X1 and X2, at least one of the said first and second load capacitors 16a and 16b is the variable capacitance capacitor, and DC cutoff capacitors 21 and 22 are connected to the side of the connecting terminal, to which the variable capacitance capacitor is connected at least, between an input terminal Xg of the said inverter 13 and the first connecting terminal X1 and between an output terminal Xd of the said inverter 13 and the second connecting terminal X2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation control circuit for an oscillation circuit using a crystal oscillator, a ceramic oscillator or the like used in electronic equipment and the like. Thus, it is possible to reduce the size, weight, and cost of electronic devices and the like.

[0002]

2. Description of the Related Art FIG. 12 shows an oscillation circuit of a standard crystal unit. As shown in the figure, this oscillation circuit is a Colpitts type oscillation circuit, and both ends of the crystal unit 1 are connected to a connection terminal X.
1 and X2, are connected to load capacitors 2a and 2b, and a CMOS inverter 3 and its feedback resistor 4 are connected to these connection terminals X1 and X2. The output terminal of the CMOS inverter 3 and the crystal unit 1
A terminal X2 is provided with a damping resistor 5.

In such an oscillation circuit, the oscillation frequency is determined by the inductance and resistance of the equivalent circuit of the crystal unit 1 and the capacitance of the load capacitors 2a and 2b.

On the other hand, an oscillation control (Voltage Cont
rol Xtal Oscillator; VCX
O) Circuits are known. FIG. 13 shows an example of a conventional VCXO circuit.

As shown in FIG. 13, terminals at both ends of the crystal unit 1 are connected to a series capacitor of a variable capacitor 6a and a DC blocking capacitor 9a and a DC capacitor 6b, respectively, via connection terminals X1 and X2. It is connected to the series capacitor of the capacitor 9b. The connection terminals X1 and X2 are further connected to a circuit including the CMOS inverter 3 and its feedback resistor 4 and damping resistor 5. On the other hand, connection nodes Pg and Pd between the variable capacitors 6a and 6b and the DC blocking capacitors 9a and 9b are connected to the control voltage terminal 8 via the bias resistors 7a and 7b.

In such a configuration, by changing the control voltage Vc applied from the control voltage terminal 8, the capacitances of the variable capacitance capacitors 6a and 6b are changed, and the above-mentioned series capacitance which becomes the load capacitance of the crystal unit 1 is extended. The capacitance of the capacitor changes, so that the oscillation frequency can be changed.

[0007]

In the configuration shown in FIG. 12, DC blocking capacitors 9a and 9b are provided to cut off the DC voltage from control voltage terminal 8 and the DC voltage from inverter 3.
Is provided. However, since the DC blocking capacitors 9a and 9b and the variable capacitance capacitors 6a and 6b are respectively arranged in series,
In order to directly reflect the change in the capacitances of the variable capacitors 6a and 6b, the capacitance of the DC blocking capacitors 9a and 9b should be at least 10% of the maximum capacitance of the variable capacitors 6a and 6b.
Must be about twice as large. For example, when the capacitance of the variable capacitance capacitors 6a and 6b changes the control voltage Vc applied from the control voltage terminal 8 to about 0 to 5V, the capacitance becomes 7p.
When changing in the range of F to 20 pF, the capacitance of the DC blocking capacitors 9a and 9b needs to be at least about 200 pF.

The configuration in which such a large capacitor is provided is a major bottleneck in miniaturizing the element.
For example, in the case of a semiconductor integrated circuit, 200
A single pF capacitor requires an area of 0.5 mm square, but there is a demand to fit the entire oscillator circuit except for the crystal unit 1 in 1 mm square in order to reduce the area of the chip that constitutes the oscillator circuit. There is.

In view of such circumstances, the present invention provides an oscillation control circuit capable of reducing a large-capacity capacitor and miniaturizing a chip area, thereby reducing the size, weight, and cost of an electronic device or the like. The task is to provide

[0010]

According to a first aspect of the present invention, there is provided an oscillation control apparatus capable of controlling an oscillation frequency of an oscillation circuit including an oscillator connected to a first or second connection terminal. A circuit comprising: an inverter functioning as an amplifier of the oscillation circuit; and first and second load capacitors connected to the first and second connection terminals, respectively, wherein the first and second load capacitors are provided. At least one of the load capacitors is a variable capacitor,
Between the input terminal of the inverter and the first connection terminal and between the output terminal of the inverter and the second connection terminal, at least on the connection terminal side to which the variable capacitor is connected, a DC blocking capacitor is provided. The oscillation control circuit is characterized by being connected.

A second aspect of the present invention is the oscillation control circuit according to the first aspect, wherein the second connection terminal is connected to an output terminal of the inverter via a damping resistor.

A third aspect of the present invention is the oscillation control circuit according to the first or second aspect, wherein the second load capacitor is a fixed capacitor.

According to a fourth aspect of the present invention, in the third aspect, the DC cutoff capacitor is connected only between the input terminal of the inverter and the first connection terminal. In the circuit.

A fifth aspect of the present invention is the oscillation control circuit according to the first or second aspect, wherein the first load capacitor is a fixed capacitor.

According to a sixth aspect of the present invention, in the fifth aspect, the DC blocking capacitor is connected only between the output terminal of the inverter and the second connection terminal. In the circuit.

According to a seventh aspect of the present invention, in any one of the first to fourth aspects, the input terminal of the inverter is connected to the first terminal.
Wherein the capacitance of the DC blocking capacitor connected between the connection terminals is about 5 to 30 times the input capacitance of the inverter viewed from the input terminal.

According to an eighth aspect of the present invention, there is provided the first, second, third,
In the fifth, sixth or seventh aspect, the capacity of the DC cutoff capacitor connected between the output terminal of the inverter and the second connection terminal is such that the DC cutoff capacitor is connected in parallel with the second load capacitor. The oscillation control circuit is characterized in that the equivalent capacitance when it is assumed that the second capacitance is not more than one fifth of the minimum capacitance of the variable region of the second load capacitor.

A ninth aspect of the present invention is the oscillation control circuit according to any one of the first to eighth aspects, wherein the inverter is a CMOS inverter.

According to a tenth aspect of the present invention, in any one of the first to ninth aspects, the variable capacitor is a MOS capacitor, and the MOS capacitor is a first conductive type semiconductor corresponding to one capacitor electrode. A conductive layer serving as the other capacitor electrode over the substrate with an insulating film interposed therebetween, and a structure having a second conductivity type impurity region in the vicinity of the conductive layer; and a control voltage is applied to the conductive layer. An oscillation control circuit has a function of changing the capacitance value when applied.

According to an eleventh aspect of the present invention, in the tenth aspect, a reverse voltage of a PN junction is applied to the second conductive type impurity region with respect to the first conductive type semiconductor substrate. Oscillation control circuit.

A twelfth aspect of the present invention is the oscillation control circuit according to the eleventh aspect, wherein the reverse voltage is applied via a bias resistor.

A thirteenth aspect of the present invention is directed to the eleventh or twelfth aspect.
In the oscillation control circuit, the power supply voltage of the oscillation control circuit is used as the reverse voltage.

According to a fourteenth aspect of the present invention, the oscillation control circuit according to any one of the first to thirteenth aspects comprises a semiconductor integrated circuit formed on the same semiconductor substrate, and is connected to both terminals of the vibrator. The oscillation control circuit has the first and second connection terminals for performing the above operation.

A fifteenth aspect of the present invention is the oscillation control circuit according to any one of the first to fourteenth aspects, wherein the vibrator is a quartz vibrator.

According to the present invention, in an oscillation control circuit for controlling the oscillation frequency of an oscillation circuit using a variable capacitance capacitor, a capacitor is provided at a predetermined position to cut off the oscillation circuit in a DC manner from a voltage applied to the variable capacitance capacitor. This significantly reduces the required capacity of the capacitor. As a result, the chip area of a semiconductor integrated circuit is significantly reduced, and the size, weight, and cost of the electronic device can be reduced.

[0026]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to one embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit 10 has all the elements except the crystal resonator 1 mounted thereon. That is, the semiconductor integrated circuit 10 includes the terminals X1 and X2 for connecting both ends of the crystal unit 1, and includes the CMOS inverter 13 and the feedback resistor 14. A damping resistor 1 is provided between the output terminal of the CMOS inverter 13 and the terminal X2 of the crystal unit 1.
5 are provided.

On the other hand, variable capacitance capacitors 16a and 16b are connected to terminals X1 and X2, and control voltage terminals 18 for inputting an external voltage via load resistors 17a and 17b are connected to the variable capacitance capacitors 16a and 16b. Is connected.

In the present embodiment, the first and second terminals X1 and X2 are connected between the connection terminals X1 and X2 of the crystal unit 1 and the input terminal Xg and the output terminal Xd at both ends of the CMOS inverter 13, respectively. DC blocking capacitors 21 and 22 are connected. Here, the positional relationship between the second DC blocking capacitor 22 and the damping resistor 15 may be reversed. Note that the damping resistor 15 does not necessarily need to be provided.

Here, the first and second DC cut-off capacitors 21 and 22 may have a significantly smaller capacity than the DC cut-off capacitors 9a and 9b of the conventional circuit having a capacitance of 200 pF. They were 10 pF and 50 pF, respectively.

The operation and effect of the first and second DC blocking capacitors 21 and 22 in the semiconductor integrated circuit 10 will be described.

The first DC blocking capacitor 21 provided on the input terminal Xg side of the CMOS inverter 13 has a CMO
The input terminal Xg of the S inverter 13 and the connection node Pg between the variable capacitor 16a and the load resistor 17a are cut off in a DC manner, and the voltage fluctuation appearing on the variable capacitor 16a is transmitted to the input terminal Xg. If it is assumed that the input impedance of the CMOS inverter 13 from the terminal X1 is infinite, the voltage fluctuation at the terminal X1 is transmitted to the input terminal Xg without attenuating even if the first DC cutoff capacitor 21 has a very small capacitance. You. Actually, the capacity of the first DC cut-off capacitor 21 is equal to the CM from the input terminal Xg side.
Since the input capacitance of the OS inverter 13 is generally considered to be about 1 pF, it is at least as large as 5 pF or more.
It may be selected up to about 0 times, but preferably 5 to 30 times.
It should be about twice. From the viewpoint of blocking DC voltage, for example, a capacitance of 1 pF is sufficient.

On the other hand, the second DC blocking capacitor 22 provided on the output terminal Xd side of the CMOS inverter 13
The output terminal Xd of the CMOS inverter 13 and the connection node Pd between the variable capacitor 16b and the load resistor 17b are cut off in a direct current manner, and the equivalent capacitor 22A having a small capacitance is connected to the variable capacitor 16b by equivalent circuit conversion as described later. (See FIG. 7) act as if they are connected in parallel. Therefore, the second DC blocking capacitor 22
Means that the capacitance of the variable capacitance capacitor 16b, which is the load capacitance of the crystal unit 1, is raised by this minute capacitance.

The equivalent circuit conversion will be described in detail below.

First, FIG. 4 shows that the variable capacitance capacitors 16a and 16b of the circuit diagram of FIG.
A circuit diagram showing capacitors 31 and 32 having d is shown. FIG. 5 shows an AC equivalent circuit of this circuit. The circuit from the first DC blocking capacitor 21 to the feedback resistor 14 is omitted.

In the equivalent circuit of FIG. 5, the CMOS inverter 13 is replaced by a voltage source 33, which has a resistance Rd.
Is connected to one end of a second DC blocking capacitor 22 having a capacitance Cpd via a connection node X3. The other terminal of the second DC blocking capacitor 22 is connected to one terminal of the crystal unit 1 via a connection terminal X2, and the terminal X2 has a coil of an inductance Xe, which is equivalently replaced by the crystal unit 1. 35 and a resistor 36 having a resistance value Re are connected in series. Note that a capacitor 32 having a capacitance Cd is connected in parallel to the connection node X2, and a capacitor 31 having a capacitance Cg is connected to the other terminal of the crystal unit 1 via a connection terminal X1.

The circuit shown in FIG. 6A is obtained by extracting a circuit as viewed from the power supply side from the connection terminal X2 in the equivalent circuit of FIG. Here, assuming that the voltage source 33 is a current source, FIG.
Is equivalently replaced by the circuit shown in FIG. That is, the current source 33A
A resistor 15A having a resistance value Re and a capacitor 2 having a capacitance Ce.
2A is a circuit connected in parallel.

When the current source 33A shown in FIG. 6B is converted into a voltage source again, the circuit shown in FIG. 7 is obtained. That is, the resistor 15A is connected in series to the voltage source 33B,
2A is reconverted to a state of being connected in parallel.

Here, assuming that the overall impedance in FIG. 6A is Z and the oscillation frequency of the circuit is f, the following equation (Equation 1) is established. In FIG. 6B, the following equation (Equation 2) is obtained. Holds.

[0040]

(Equation 1)

Here, ω = 2πf

[0042]

(Equation 2)

Since FIG. 6A and FIG. 6B are equivalent, the resistance Re and the capacitance Ce are expressed by the following equation (Equation 3).

[0044]

(Equation 3)

Assuming that approximation of ω ² C ² R ²成 り 1 holds, Re ≒ R. Therefore, Ce and Ie are expressed by the following equations (Equation 4).

[0046]

(Equation 4)

Similarly, if the above approximation holds, FIG.
Is expressed by the following equation (Equation 5).

[0048]

(Equation 5)

Here, Rd = R = 1KΩ, Cpd = 50
When an actual numerical value is calculated with pF, f = 27 MHz, the following is obtained.

[0050]

(Equation 6)

From the above results, the second DC cutoff capacitor 22 is equivalent to a state where the capacitor 22A having the capacitance Ce described above is connected in parallel to the variable capacitance capacitor 16b. Therefore, as the load capacitance of the crystal unit 1 on the connection terminal X2 side, the capacitance of the variable capacitance capacitor 16b and the minute capacitance of the equivalent parallel capacitor 22A (0.69 pF in the above-described example) are raised.

FIG. 8 shows the capacitance Ce of the capacitor 22A and the resistance Re of the resistor 15A of the equivalent circuit when the capacitance Cpd of the second DC cutoff capacitor 22 is changed. Thus, as the capacitance of the second DC cutoff capacitor 22 is appropriately increased, the capacitance C of the capacitor 22A of the equivalent circuit connected in parallel with the variable capacitance capacitor 16b
e is smaller, which is preferable. At this time, the resistance value Re also approaches 1 KΩ, which is preferable.

The second DC blocking capacitor 22 as described above
Is smaller than the minimum capacitance of the variable region of the second variable capacitance capacitor 16b by 1/5 or less, and preferably 1/10 of the minimum capacitance of the variable region of the second variable capacitance capacitor 16b.
It is desirable to set as follows. For example, if the minimum capacitance of the second variable capacitance capacitor 16b is 7 pF, in the above-described example, the equivalent capacitance Ce is 0.69 pF, which is 1/10 or less.

The case where the capacitance Cpd of the second DC blocking capacitor 22 is 50 pF, that is, the capacitance Ce of the capacitor 22A of the equivalent circuit is 0.69 pF, and the capacitance of the variable capacitor 16b is changed by the control voltage Vc. The capacitance Cd of the variable capacitor 16b and the capacitor 2
FIG. 9 shows a change in the combined capacity of the 2A capacity Ce. In the figure, the combined capacitance Cdef (New) is raised by Ce and changes with respect to the capacitance Cd. The change in the combined capacitance when a capacitor of 200 pF is connected as shown in the section of the prior art is shown as Cdef (Conv). From this figure, it can be seen that the DC blocking capacitor of 50 pF in this embodiment has a function substantially equivalent to the DC blocking capacitor of 200 pF in the conventional embodiment.

In the oscillation control circuit according to the present embodiment described above, whether the variable capacitance capacitor is attached to the input side or the output side of the inverting amplifier (inverter), it is extremely difficult to compare with the DC blocking capacitor of the conventional circuit. May be provided with a very small DC blocking capacitor. Thereby, particularly when a circuit other than the crystal unit 1 is a semiconductor integrated circuit, a remarkable area reduction can be achieved.

For example, the 200p described in the section of the prior art
Each capacitor of F requires an area of about 0.5 mm square, but in the above-described embodiment, the entire control circuit can be integrated to about 1 mm square.

In the above-described embodiment, two variable capacitance capacitors are provided. However, if a sufficient capacitance change can be obtained, one of them may be omitted and a fixed capacitor may be used. DC blocking capacitors can also be omitted. These examples are shown in FIGS.
2 omits the variable capacitor 16b and provides a fixed capacitor 24, and FIG. 3 omits the variable capacitor 16a and replaces the fixed capacitor 23b.
Is provided. 2 and FIG.
The same reference numerals are given to members having the same functions as those described above, and overlapping description will be omitted.

Here, the minute variable capacitor is not particularly limited as long as its capacitance changes by changing the applied voltage. For example, a so-called varicab diode can be used. In this case, the oscillation control circuit of the present embodiment has another excellent advantage. When the oscillation control circuit is realized by a semiconductor integrated circuit, the terminals X1 and X2 are connection terminals to a crystal unit which is an external component of the semiconductor integrated circuit, and these terminals need to be provided with an electrostatic protection circuit. Become. In this embodiment, as can be seen from FIG. 1, a circuit in which varicap diodes made of PN junctions are directly connected to the terminals X1 and X2, and these varicab diodes function as an electrostatic protection circuit as it is. Therefore, the static electricity protection circuits for the terminals X1 and X2 can be omitted or simplified, and stray capacitance harmful to the oscillation control circuit can be reduced.

When the oscillation control circuit is realized by a MOS semiconductor integrated circuit, it is desirable to use a new MOS varicap capacitor as described below.

FIG. 10 is a schematic sectional view showing such a new MOS type varicap capacitor. An N ⁺ -type impurity region 53 is formed in the P ⁻ -type semiconductor substrate 51, and a gate electrode 52 is provided on an insulating film 56 formed on the surface thereof.

Here, the N ⁺ -type impurity region 53 is formed by ion implantation or the like in a self-aligned manner with respect to the gate electrode 52 similarly to the source / drain region of the NMOS transistor formed in the same semiconductor substrate. For example, it is possible to adopt a structure in which the overlap (which becomes an unnecessary capacitance) is minimized while approaching the gate electrode 52.

As shown, when a + (plus) voltage is applied to the gate electrode 52, a depletion region (depletion layer) 54 is first formed near the surface in the P ^- type semiconductor substrate 51, and the thickness of the depletion layer is formed. The capacitance value decreases with increasing. Then, when the applied voltage further increases, inversion charges are formed on the P ⁻ type substrate surface (strong inversion state), and the growth of the depletion layer is saturated,
At the same time, the phenomenon of the capacitance value stops. However, for example, by providing the N ⁺ -type impurity region 53 biased to Vdd (= 5 V) as described above,
It becomes possible to suppress the appearance of inversion charges until a thicker depletion layer grows. Therefore, the variable width of the capacitance value can be increased. V of N ⁺ type impurity region 53
When the bias to dd is performed via the resistor 58, a further effect can be obtained. The bias resistor 58 is connected to Vdd which is instantaneously applied to the gate electrode 52 during oscillation of the circuit.
Even for a voltage that greatly exceeds the voltage, the formation of inversion charges appearing on the surface of the P ⁻ -type substrate can be suppressed. Therefore,
Thanks to the bias resistor 58, even when the oscillation amplitude applied to the gate electrode 52 increases, the new MOS capacitor operates stably without showing an unstable change in the capacitance. Note that the bias resistor 58 may be omitted.

FIG. 11A is a schematic graph for explaining the CV characteristics of the new MOS type capacitor. The horizontal axis indicates the DC bias voltage (V) of the gate electrode 52, and the vertical axis indicates the relative capacitance of the new MOS capacitor with respect to the capacitance of 1.0 during accumulation.

When the substrate is of the P ⁻ type, the ordinary MOS type capacitor has a characteristic as shown by a curve 62 at a measurement frequency of 1 MHz, for example, with respect to the bias voltage applied to the gate electrode. Has stopped decreasing and is saturated. On the other hand, the new MOS type capacitor has the above-described structure and effect, and thus exhibits a decreasing characteristic in which the capacitance is not saturated as shown by a curve 63.

FIG. 11 (b) shows a new MOS type varicap capacitor and C of a varicap diode with a PN junction.
It is a typical graph which compares -V characteristic. The horizontal axis represents the applied voltage (V), and the vertical axis represents the capacitance per unit area.
The characteristic is a curve 72. By adopting such a MOS capacitor configuration, it is possible to obtain a change rate of about 1.5 times that of the PN type in the same voltage range as shown in the figure. Further, the CV characteristic of the PN junction has a problem that, when the applied voltage is slightly negative (positive side as a diode), a forward current flows and does not function as a pure capacitance. MO
It goes without saying that there is no such problem in S.

In the above embodiment, a CMOS inverter is used as an inverter, but it is needless to say that another inverter may be used.

As the vibrator, a ceramic vibrator or the like may be used in addition to the crystal vibrator.

In the above-described embodiment, the external control voltage Vc is used as it is as the bias voltage of the variable capacitor. However, the external control voltage Vc is divided by a resistor circuit, or other analog circuit is used. After the conversion, the bias voltage of the variable capacitor may be used.

[0069]

As described above in detail with the embodiment of the present invention, the oscillation control circuit of the present invention can greatly reduce the capacity of the DC blocking capacitor used as compared with the conventional control circuit. The area can be reduced, whereby the size and weight of the electronic device and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an oscillation control circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an oscillation control circuit according to another embodiment of the present invention in which a variable capacitor is arranged only on the input side of an inverter.

FIG. 3 is a circuit diagram obtained by modifying an oscillation control circuit according to another embodiment of the present invention in which a variable capacitor is arranged only on the output side of an inverter.

FIG. 4 is a circuit diagram obtained by modifying the oscillation control circuit according to the embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of the circuit diagram of FIG.

6 is a circuit diagram showing the equivalent circuit on the power supply side in FIG. 5 and its equivalent conversion.

FIG. 7 is a circuit diagram in which the power supply circuit of FIG. 6 is converted again.

FIG. 8 is a graph showing equivalent capacitance and equivalent resistance when the capacitance of a second DC blocking capacitor is changed.

FIG. 9 is a graph showing an evaluation of a combined capacitance of a control circuit according to an embodiment of the present invention.

FIG. 10 is a schematic sectional view showing a novel MOS type varicap capacitor that can be used in the present invention.

FIG. 11 is a schematic graph illustrating CV characteristics of a novel MOS varicap capacitor that can be used in the present invention.

FIG. 12 is a circuit diagram illustrating an example of a general crystal oscillation circuit.

FIG. 13 is a diagram showing an oscillation control circuit according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Crystal oscillator 10 Semiconductor integrated circuit 13 CMOS inverter 14 Feedback resistance 15 Damping resistance 16a, 16b Variable capacitance capacitor 17a, 17b Load resistance 18 Control voltage terminal 21, 22 DC cutoff capacitor

Claims (15)

[Claims] 1. An oscillation control circuit capable of controlling an oscillation frequency of an oscillation circuit including an oscillator connected to a first or second connection terminal, wherein an inverter functioning as an amplifier of the oscillation circuit; First and second load capacitors respectively connected to a second connection terminal, wherein at least one of the first and second load capacitors is a variable capacitor, and A DC blocking capacitor is connected between an input terminal and the first connection terminal and between an output terminal of the inverter and the second connection terminal, at least on a connection terminal side to which the variable capacitor is connected. An oscillation control circuit, characterized in that: 2. The oscillation control circuit according to claim 1, wherein said second connection terminal is connected to an output terminal of said inverter via a damping resistor. 3. The oscillation control circuit according to claim 1, wherein the second load capacitor is a fixed capacitor. 4. The oscillation control circuit according to claim 3, wherein the DC blocking capacitor is connected only between an input terminal of the inverter and the first connection terminal. 5. The oscillation control circuit according to claim 1, wherein the first load capacitor is a fixed capacitor. 6. The oscillation control circuit according to claim 5, wherein the DC blocking capacitor is connected only between an output terminal of the inverter and the second connection terminal. 7. The inverter according to claim 1, wherein a capacity of a DC blocking capacitor connected between an input terminal of the inverter and the first connection terminal is equal to an input of the inverter as viewed from the input terminal. An oscillation control circuit having a capacitance of about 5 to 30 times. 8. The DC cut-off capacitor according to claim 1, wherein the DC cut-off capacitor connected between the output terminal of the inverter and the second connection terminal is connected to the DC cut-off capacitor. The equivalent capacitance when considered as being connected in parallel with the second load capacitor is set to be equal to or less than one fifth of the minimum capacitance of the variable region of the second load capacitor. Characteristic oscillation control circuit. 9. The oscillation control circuit according to claim 1, wherein said inverter is a CMOS inverter. 10. The variable capacitance capacitor according to claim 1, wherein the variable capacitance capacitor is a MOS capacitor, and the MOS capacitor is provided on a first conductivity type semiconductor substrate corresponding to one capacitor electrode via an insulating film. A conductive layer serving as the other capacitor electrode, having a structure having a second conductivity type impurity region adjacent to the conductive layer, and having a capacitance value obtained by applying a control voltage to the conductive layer; An oscillation control circuit having a function of changing the oscillation frequency. 11. The oscillation control circuit according to claim 10, wherein a reverse voltage of a PN junction is applied to said second conductivity type impurity region with respect to said first conductivity type semiconductor substrate. 12. The oscillation control circuit according to claim 11, wherein the reverse voltage is applied via a bias resistor. 13. The oscillation control circuit according to claim 11, wherein a power supply voltage of an oscillation control circuit is used as the reverse voltage. 14. The oscillation control circuit according to claim 1, wherein said oscillation control circuit comprises a semiconductor integrated circuit formed on the same semiconductor substrate, and said first and second oscillation control circuits are connected to both terminals of said vibrator. An oscillation control circuit having two connection terminals. 15. The oscillation control circuit according to claim 1, wherein the vibrator is a crystal vibrator.