JPS6034847B2 - crystal oscillation circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a crystal oscillation circuit used in electronic watches, etc.
In particular, the present invention aims to provide an oscillation circuit with low current consumption and low oscillation start voltage.

One of the conventional crystal oscillation circuits used in electronic watches is the one shown in FIG. 1. This oscillation circuit consists of a P-channel transistor 1 and a resistor Rb as bias means.
an amplifier circuit comprising a feedback resistor Rf connected between the input and output of an inverter, and a crystal oscillator x'tal and a capacitor CD, which constitute a positive feedback circuit between the input and output of this amplifier circuit.
The main oscillator circuit consists of a main oscillation circuit consisting of a CG, and an output increasing circuit B consisting of a complementary inverter consisting of a P-channel transistor 4 and an N-channel transistor 5. The reason for using a complementary inverter for amplification is that in electronic watches, the circuit that separates the oscillation output is usually done by complementary connection of field effect transistors, so it is necessary to match the logic level to the operating level of the complementary field effect transistors. It's because of sex. In this conventional oscillation circuit, in order to reduce the oscillation current, Rb is increased,
When the signal amplitude at point D and the through current from 1 to Rb are reduced, the DC bias level of D becomes close to the threshold voltage of 1.

The logic transition level of the output amplifier circuits B4 and B5 is as follows:
Normally, it is half of the power supply voltage, that is, about 1 VDD/2, so if Rb is increased as described above, this transition level and the DC bias level at point ○ will not match, and the subsequent circuit will not be able to drive. The higher the value, the greater this backward movement. In view of this, it is an object of the present invention to provide an oscillation circuit that can match the transition level of the complementary circuit even if Rb is increased, and further provides a stable oscillation output regardless of the level of the power supply voltage. For this purpose, the present invention configures an oscillation circuit configuration consisting of a main oscillation circuit A and an output amplifier circuit B, as shown in FIG.

The level conversion circuit C converts the DC bias level of the oscillation waveform that is biased toward the function value of the transistor of one channel (the P channel in the example shown in Figure 1) to a level that is biased toward the function value of the opposite channel (N channel). , superimpose the AC component of the oscillation output of the main oscillation circuit on its DC level and input it to the opposite channel (N channel) transistor of B,
One channel (P channel) transistor has
Push-pull amplification is achieved by directly inputting the output of the main oscillation circuit or an input using equivalent means. Examples of the present invention embodying this idea are shown in FIGS. 2a and 2b and 3a and 3b, and will be described below. In FIG. 2a, the main oscillation circuit A has substantially the same configuration as in FIG. 1.

However, in order to facilitate integration with other circuits such as frequency division and drive circuits of an electronic timepiece, the resistors Rf and Rb are constructed of field effect transistors. The P-channel transistor 3, which is equivalent to Rf, has a large Rb and the DC bias level at point D is close to the threshold value VGTP of 1, so it is used in one channel rather than in parallel with the N-channel transistor. Further, Rb is constituted by an equivalent N-channel transistor 2, and the bias current to the transistor 1 is extremely small. This small bias current makes the oscillation amplitude small, and the through current and capacitor charging/discharging current also become small. This small oscillation signal is input to the level conversion circuit C. If the conductance and threshold voltage of the P-channel transistor 6 and the N-channel transistor 7 are almost equal, the DC bias level of E is such that the current potential of E when viewed from 1 VDD to the ground potential is in the direction from the ground potential to -VDD. It is determined to be approximately equal to the DC potential of ○ seen in . The external conductance of the 10 transfer transistors is extremely 4.
It is designed to act as a high resistance and reduce the DC potential at point F to E.
Bias the potential at a point. Further, at point F, the AC signal component from point D is superimposed with the capacitor CN cutting off the DC component.
That is, the AC component at E is subjected to a reduction filter of 10 and CN'. Furthermore, the transfer transistor 10
has a high resistance, which prevents point D from being connected to point F, which becomes a low impedance load. Point F is connected to the gate of N-channel transistor 9 of output amplifier circuit B, and point D is connected to the gate of P-channel transistor 8. Each DC bias level of 8 and 9 is near its dark value VOTP, VGTN.

Figure 2b shows the waveforms of D, E, F and omt in Figure 2a.
Shown below. In FIG. 2b, VGTP and VGTN indicate the threshold voltages of a P-channel transistor and an N-channel transistor, respectively. The voltage waveform at point D is VOT
It is a waveform that oscillates around P, and the voltage waveform at point F is a waveform that oscillates around voltage VGTN at point E.
Since the AC signals at points D and F have the same phase waveforms as shown in FIG. B is amplified almost in a push-pull operation, and the output becomes as shown at 0ut in the figure. Output terminal Out
Since it becomes an input to the gate of another complementary type transistor in the integrated circuit, its parasitic capacitance is small, a swing up to the power supply voltage can be obtained, and the logic level can be perfectly matched with the complementary type transistor. In addition, as all circuits A, C, and B operate near the threshold values of their respective transistors, the current consumption is small, and furthermore, the logic level of the complementary circuit represented by the complementary inverter is consistent. It is stable due to its integrity and operates with extremely small oscillation amplitude.
There is a characteristic advantage that the oscillation starting voltage can also be lowered. By the way, in Fig. 2, the main oscillation circuit outputs the output from point D, but instead of this, the signal at gate point 1 can be output and connected to gates 6 and 8. The same effect as above can be obtained.

Next, FIG. 3, which is another embodiment, will be explained.

The main oscillation circuit A has a gate of 1 connected to a capacitor Ct connected in series to Xtal. The capacitor Ct is for cutting the DC component, and can transmit only the AC component to the connection point of the capacitors CP and CN, which will be described later. The gate capacitance CG is that X'ta! It is connected between the node 1 of Ct and the ground point. The level conversion circuit C has its input taken from the gate point 1, and a DC bias level close to the dark value VGTP of the P channel transistor is applied to the point G via the P channel transistor 11 of the transfer transistor. The DC bias level at point H, which is close to the threshold value VGTP of the P-channel transistor, is level-converted by the P-channel transistor 7 to become a DC bias level close to the threshold value VGTN of the N-channel transistor, and is transferred to point F via the N-channel transistor 10. Given. The oscillation output of the main oscillator circuit is taken from one point, and the oscillation AC signal is superimposed and input to the gate of the P-channel transistor 8 of the output amplifier circuit B at the point G using the capacitor CP, and then input to the gate of the N-channel transistor 9. The oscillating AC signal is superimposed and input to point F by capacitor CN. The transistors 0 and 11 function as high resistances as in FIG. Figure 3b shows the voltage waveforms at each part in Figure 3a.The voltage waveforms at points 1 and 3 are waveforms that oscillate around VGTP, and the voltage waveform at point F is the voltage waveform at point E, which is VGTN. It becomes a waveform that vibrates around the center.
Since the waveforms at points F and G are in phase, output amplifier circuit B amplifies them by push-pull operation. Since Ct, capacitances Cp, and Cn are monolithically formed within the integrated circuit as shown in No. 51a, even if the connection point 1 with X'GI is in a high temperature state outside the integrated circuit, there is no transistor at that point. Since the gate is not connected, the bias point does not fluctuate due to leakage, and stable oscillation is maintained.

Furthermore, CG and CD can also be formed monolithically. To explain FIG. 4a, 12 is an N-substrate, 1
3 is P+ diffusion layer, 14 is Sio, gate film, 15 is Si
o is a field film, 16 is a gate electrode, and 17 is a contact between 13 and a metal, which is equivalently as shown in Fig. 4b.The capacitance is 18>19, and 12 is at ground potential, so for example, Ct, Cp. , CN, add 16 to each H, G, F
13 (17) may be used as one terminal (FIG. 3a) or a D terminal (FIG. 2a).

The remaining capacity 19 then becomes part of the CG (FIG. 3a) or the CD (FIG. 2a). Also, in order to form CG and CD, it is sufficient to set 17 to the ground potential and 16 to the node potential with the X' field. However, in Fig. 3a, 6
The input at point H, which is the gate and drain input of 11, is
Similar effects can be obtained by inputting from point D as in the explanation of FIG. Furthermore, the structural advantages of FIG. 3 are almost the same as those of FIG. 2. Furthermore, the level conversion circuit in FIG. 3a may convert the level at point E again to achieve the DC bias level at point G, as shown in FIG. If the conductance and threshold voltage of the N-channel transistor 21 and the P-channel transistor 20 are approximately equal, a DC bias level close to the threshold of the N-channel transistor will be converted to a DC bias level close to the threshold of the P-channel transistor. be. The present invention as described above makes it possible to set the oscillation output signal to a voltage level that can drive a circuit using other complementary MOC transistors even when the MOC transistor for excitation of a crystal resonator is either a P-channel type or an N-channel type. This makes it extremely effective as a crystal oscillation circuit formed on the same substrate as other logic circuits such as electronic watches.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional oscillation circuit. FIG. 2a is a diagram showing an embodiment of the oscillation circuit of the present invention. FIG. 2b is a waveform diagram thereof. FIG. 3a is a diagram showing another embodiment of the oscillation circuit of the present invention. FIG. 3b is a waveform diagram thereof. FIG. 4a is a diagram showing an example of the configuration of the capacitor used in FIGS. 2 and 3 of the oscillation circuit of the present invention on an integrated circuit. Figure 4b is Figure 4a
The figure which shows the equivalent circuit of. FIG. 5 is a diagram showing another embodiment of the level conversion circuit constituting the oscillation circuit of the present invention. Fig. 1 Fig. 2 (A) Fig. 2 (b) Fig. 3 (Q) Fig. 3 b) Fig. 5 Fig. 4 (Fig.

Claims (1)

[Claims] 1 Consists of a main oscillation section, a level conversion section, and an output amplification section. The level conversion section is composed of a crystal resonator connected between a gate electrode and a drain electrode, and the level conversion section is connected in series with a second MOS transistor of a first polarity that receives the signal from the main oscillation section and the second MOS transistor. The output amplification section includes a fourth MOS transistor of the first polarity, which receives the output of the main oscillation section, and a fourth MOS transistor of the first polarity, the gate electrode and the drain electrode of which are connected in common. 4MOS
A fifth MOS transistor of a second polarity is biased with the potential of a common connection point between the gate electrode and the drain electrode of the third MOS transistor connected in series with the transistor, and receives the output signal of the main oscillation section as input. A crystal oscillation circuit characterized by: