JP2969419B2 - Oscillation integrated circuit and oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation integrated circuit and an oscillation circuit.

[0002]

2. Description of the Related Art At present, in an oscillation integrated circuit used as a reference clock generation source in a clock or the like, a piezoelectric vibrator such as a crystal vibrator is connected between input / output terminals of a CMOS inverter, and furthermore, an input / output terminal of the CMOS inverter is used. A feedback resistor is connected between them. Such devices include those in which a MOS transistor constitutes a feedback resistor.
There is something like that shown in This is achieved by connecting the input / output terminals of a CMOS inverter 22 having a crystal resonator 21 externally connected between an input terminal in and an output terminal out via a P-channel MOS transistor 23p and an N-channel MOS transistor 23n. is there. The gates of these MOS transistors 23n and 23p are connected to a power supply terminal VDD (for example, + 5V) and a power supply terminal V
SS (eg, 0V), which act as feedback resistors due to their on-resistance. In the figure, reference numeral 24 denotes an output buffer, which is a CMOS inverter 2
2 to output an oscillation output signal to a subsequent stage (not shown). Further, xt and xtb are external terminals for externally attaching the crystal resonator 21.

[0003]

SUMMARY OF THE INVENTION In such a case,
The gates of the MOS transistors 23n and 23p are connected to a power supply terminal via a resistor r. The resistance value of the resistor r cannot be increased so much as to increase the chip size of such an oscillation integrated circuit. In addition, since the crystal unit 21 is externally attached to the CMOS inverter 22, the input terminal in and the output terminal out of the CMOS inverter 22 are exposed to external static electricity. Therefore, for example, when an overvoltage is applied to the input terminal in or the output terminal out by external static electricity, the MOS transistor 23
Often, the n or 23p gate was destroyed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an oscillation integrated circuit and an oscillation circuit having excellent durability against static electricity without increasing the circuit area.

[0005]

According to the present invention, there is provided an oscillation integrated circuit comprising a CMOS inverter, wherein a piezoelectric vibrator is externally connected between input and output terminals of the CMOS inverter.
A feedback resistor composed of a MOS transistor is connected between the input and output terminals of the OS inverter, and the gate of the MOS transistor is held at a specific potential via a second MOS transistor.

In an oscillator circuit comprising a CMOS inverter and a load capacitance connected to each of an input terminal and an output terminal of the CMOS inverter and a piezoelectric vibrator connected between input and output terminals of the CMOS inverter, A feedback resistor comprising a MOS transistor is connected between the input / output terminals of the
The gate of the MOS transistor is held at a specific potential via the transistor.

With the above, the above object is achieved.

[0008]

Next, an embodiment of the present invention will be described. FIG. 1 is an electric circuit diagram showing the configuration of the present embodiment. In FIG. 1, reference numeral 1 denotes a CMOS inverter, which is connected between an input terminal IN and an output terminal OUT of the CMOS inverter 1 via external terminals XT and XTB. A quartz oscillator 2 as a piezoelectric oscillator is externally attached. Although not shown, the input terminal I
A capacitor as a load capacitance is connected to N and the output terminal OUT. 3n and 3p are N-channel type,
It is a P-channel type MOS transistor. The input terminal IN and the output terminal OUT of the CMOS inverter 1 are connected via the MOS transistors 3n and 3p, and these MOS transistors 3n and 3p constitute a feedback resistor 3. Reference numerals 4n and 4p denote N-channel and P-channel MOS transistors, respectively, which are second MOS transistors. The drains of the MOS transistors 4n and 4p are connected to the gates of the MOS transistors 3p and 3n, respectively.
The sources of 4p are the power supply terminals VSS (0v) and VD, respectively.
D (5v), and the gates are connected to power terminals VDD and VSS via a resistor R, respectively. By appropriately setting the voltage applied to the gates of these MOS transistors 4n and 4p or the transistor size such as the gate length and gate width, the MOS transistors 4n and 4p can be used.
The ON resistance of 4p can be set to a desired value, and here, compared to a resistance (for example, composed of a diffusion resistance or the like) connected to the gate of a MOS transistor that forms a feedback resistance in a conventional integrated circuit for oscillation. It is set to a large value.
Reference numeral 5 denotes an output buffer, which is a CMOS inverter 1
, An oscillation output signal is sent to the subsequent stage (not shown). Here, the above configuration is integrated on the same IC substrate except for the crystal unit 2. However, the present invention is not limited to this, and the output buffer 5 may be provided outside or the above-described capacitor may be externally provided. Good.

Next, the operation of this embodiment configured as described above will be described.

First, the gates of the MOS transistors 4n and 4p are connected to power supply terminals VDD and VSS via a resistor R, respectively.
, The MOS transistor 3n connects the gate to the MO
The transistor is turned on by being connected to the power supply terminal VDD via the S transistor 4p, and the MOS transistor 3
p is turned on when its gate is connected to the power supply terminal VSS via the MOS transistor 4n. As a result, the MOS transistors 3n and 3p connect the input and output terminals of the CMOS inverter, and operate as feedback resistors due to their ON resistance. In this example, an oscillating operation is performed in the same manner as in the prior art, and an oscillation output signal is generated from the output buffer 5.

Here, when a high voltage is applied to the external terminal XT due to, for example, static electricity or the like, the MO is input from the input terminal IN.
Overvoltage is applied to the power supply terminal VDD via the gate of the S transistor 3n and the drain and source of the MOS transistor 4p. At this time, the overvoltage applied to the gate of the MOS transistor 3n is reduced by the ON resistance of the MOS transistor 4p, and the gate of the MOS transistor 3n can be prevented from being destroyed. The same applies to the MOS transistor 3p.
Overvoltage applied to the gate of the MOS transistor 4n is reduced by the on-resistance of the MOS transistor 4n, and gate destruction can be avoided.

As described above, the MOS transistor 4
By appropriately setting the transistor size of n and 4p, M
The OS transistors 4n and 4p can set the ON resistance to a desired value. In addition, when this embodiment is integrated, these MOS transistors 4n and 4p can obtain a high resistance value with a small occupied area as compared with the resistance formed by a normal conductive layer. That is, in order to avoid the above-described gate destruction, an appropriate resistance value can be obtained without increasing the size of the resistor connected between the gate of the MOS transistor constituting the feedback resistor and the power supply terminal as in the conventional device. Thus, an increase in chip size can be suppressed.

Further, the present invention is not limited to the case where the feedback resistor is constituted by the two MOS transistors 3n and 3p as in the above-described embodiment.
It is also possible to provide only one of 3p, thereby forming a feedback resistor.

In the above-described embodiment, a quartz oscillator is used as the piezoelectric oscillator. However, the present invention is not limited to this. For example, a ceramic oscillator such as a PZT type or a PbTiO ₃ type may be used. Good.

[0015]

According to the present invention, it is possible to provide an oscillation integrated circuit and an oscillation circuit having excellent durability against static electricity without increasing the circuit area.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a configuration of a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CMOS inverter 2 Crystal oscillator 3 Feedback resistor 3n, 3p MOS transistor 4n, 4p MOS transistor (second MOS transistor)

Claims (2)

(57) [Claims] 1. A CM, comprising: a CMOS inverter;
An oscillation integrated circuit in which a piezoelectric vibrator is externally connected between the input and output terminals of the OS inverter, wherein a feedback resistor composed of a MOS transistor is connected between the input and output terminals of the CMOS inverter,
An oscillation integrated circuit, wherein a gate of the MOS transistor is held at a specific potential via a transistor. 2. An oscillation circuit comprising: a CMOS inverter; and a load capacitor connected to each of an input terminal and an output terminal of the CMOS inverter, and a piezoelectric vibrator connected between input and output terminals of the CMOS inverter. A feedback resistor comprising a MOS transistor is connected between the input and output terminals of the CMOS inverter, and a second MOS
An oscillation circuit, wherein a gate of the MOS transistor is held at a specific potential via a transistor.